q_sb.vhd

-- This work is licensed under a Creative Commons
-- Attribution-NonCommercial-ShareAlike 4.0 International License.
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-- Mark D. Aagaard
-- Riham AlTawy
-- Guang Gong
-- Kalikinkar Mandal
-- Raghvendra Rohit
-- Marat Sattarov
-- Nusa Zidaric
-- http://uwaterloo.ca/communications-security-lab/lwc/wage


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--- sbox ONE TRANSFORMATION Q 
------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity q_sb is 
  port
    ( i_a : in  std_logic_vector(0 to 6)
    ; o_z : out std_logic_vector(0 to 6)
   ); 
end q_sb; 

architecture rtl of q_sb is 
begin

  o_z(0) <= i_a(0) xor (i_a(2) and i_a(3));
  o_z(1) <= i_a(1);
  o_z(2) <= i_a(2);
  o_z(3) <= not i_a(3) xor (i_a(5) and i_a(6));  
  o_z(4) <= i_a(4);
  o_z(5) <= not i_a(5) xor (i_a(2) and i_a(4));
  o_z(6) <= i_a(6);

end;