Commit ef5a97bf by lwc-tester

Round 2 candidates

parent 06f56ee8

Too many changes to show.

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/* Reference implementation of ACE-128, AEAD
Written by:
Kalikinkar Mandal <kmandal@uwaterloo.ca>
Currently this implementation supports aead computation
when input message length is a multiple of 64 bits.
*/
#include<stdio.h>
......@@ -34,7 +37,7 @@ int main()
u32 *state;
int i, j;
u64 t[NUM_ITER+1], count_cc;
u64 count_cc;
u32 *plaintext, *ciphertext, *tag, *key, *nonce, *ad;
u32 plen, tlen, klen, adlen;
......@@ -88,7 +91,7 @@ int main()
for ( i = 0; i < num_parallel_inst*16; i++ )
{
k[i] = 0x0;
*(pubn+i) = 0;
*(pubn+i) = 0x0;
}
for ( i = 0; i < NUM_ITER+1; i++ )
......
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param([String]$debugfile = "");
# This powershell file has been generated by the IAR Embedded Workbench
# C - SPY Debugger, as an aid to preparing a command line for running
# the cspybat command line utility using the appropriate settings.
#
# Note that this file is generated every time a new debug session
# is initialized, so you may want to move or rename the file before
# making changes.
#
# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed
# by the name of the debug file (usually an ELF / DWARF or UBROF file).
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# Guide. Hints about additional command line parameters that may be
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param([String]$debugfile = "");
# This powershell file has been generated by the IAR Embedded Workbench
# C - SPY Debugger, as an aid to preparing a command line for running
# the cspybat command line utility using the appropriate settings.
#
# Note that this file is generated every time a new debug session
# is initialized, so you may want to move or rename the file before
# making changes.
#
# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed
# by the name of the debug file (usually an ELF / DWARF or UBROF file).
#
# Read about available command line parameters in the C - SPY Debugging
# Guide. Hints about additional command line parameters that may be
# useful in specific cases :
# --download_only Downloads a code image without starting a debug
# session afterwards.
# --silent Omits the sign - on message.
# --timeout Limits the maximum allowed execution time.
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param([String]$debugfile = "");
# This powershell file has been generated by the IAR Embedded Workbench
# C - SPY Debugger, as an aid to preparing a command line for running
# the cspybat command line utility using the appropriate settings.
#
# Note that this file is generated every time a new debug session
# is initialized, so you may want to move or rename the file before
# making changes.
#
# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed
# by the name of the debug file (usually an ELF / DWARF or UBROF file).
#
# Read about available command line parameters in the C - SPY Debugging
# Guide. Hints about additional command line parameters that may be
# useful in specific cases :
# --download_only Downloads a code image without starting a debug
# session afterwards.
# --silent Omits the sign - on message.
# --timeout Limits the maximum allowed execution time.
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<?xml version="1.0" encoding="UTF-8"?>
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param([String]$debugfile = "");
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# C - SPY Debugger, as an aid to preparing a command line for running
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# Note that this file is generated every time a new debug session
# is initialized, so you may want to move or rename the file before
# making changes.
#
# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed
# by the name of the debug file (usually an ELF / DWARF or UBROF file).
#
# Read about available command line parameters in the C - SPY Debugging
# Guide. Hints about additional command line parameters that may be
# useful in specific cases :
# --download_only Downloads a code image without starting a debug
# session afterwards.
# --silent Omits the sign - on message.
# --timeout Limits the maximum allowed execution time.
#
if ($debugfile -eq "")
{
& "D:\Program Files (x86)\IAR Systems\Embedded Workbench 8.1\common\bin\cspybat" -f "E:\Dropbox2018A\Dropbox\sLi\CCCCCC\Bit32C\ACE_32\ACE32AE1024, (0, 16)\settings\ACE32.Debug.general.xcl" --backend -f "E:\Dropbox2018A\Dropbox\sLi\CCCCCC\Bit32C\ACE_32\ACE32AE1024, (0, 16)\settings\ACE32.Debug.driver.xcl"
}
else
{
& "D:\Program Files (x86)\IAR Systems\Embedded Workbench 8.1\common\bin\cspybat" -f "E:\Dropbox2018A\Dropbox\sLi\CCCCCC\Bit32C\ACE_32\ACE32AE1024, (0, 16)\settings\ACE32.Debug.general.xcl" --debug_file=$debugfile --backend -f "E:\Dropbox2018A\Dropbox\sLi\CCCCCC\Bit32C\ACE_32\ACE32AE1024, (0, 16)\settings\ACE32.Debug.driver.xcl"
}
"--endian=little"
"--cpu=Cortex-M3"
"--fpu=None"
"-p"
"D:\Program Files (x86)\IAR Systems\Embedded Workbench 8.1\arm\CONFIG\debugger\TexasInstruments\LM3S9D96.ddf"
"--semihosting"
"--device=LM3S9D96"
"--multicore_nr_of_cores=1"
"D:\Program Files (x86)\IAR Systems\Embedded Workbench 8.1\arm\bin\armproc.dll"
"D:\Program Files (x86)\IAR Systems\Embedded Workbench 8.1\arm\bin\armsim2.dll"
"E:\Dropbox2018A\Dropbox\sLi\CCCCCC\Bit32C\ACE_32\ACE32AE1024, (0, 16)\Debug\Exe\ACE32.out"
--plugin="D:\Program Files (x86)\IAR Systems\Embedded Workbench 8.1\arm\bin\armbat.dll"
--device_macro="D:\Program Files (x86)\IAR Systems\Embedded Workbench 8.1\arm\config\debugger\TexasInstruments\LM3S.dmac"
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<DataLog>
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<ShowTimeSum>1</ShowTimeSum>
</DataLog>
<DisassembleMode>
<mode>0</mode>
</DisassembleMode>
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<FreqHi>0</FreqHi>
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</settings>
<?xml version="1.0" encoding="UTF-8"?>
<project>
<fileVersion>4</fileVersion>
<fileChecksum>2113677428</fileChecksum>
<configuration>
<name>Debug</name>
<outputs>
<file>$TOOLKIT_DIR$\config\linker\TexasInstruments\LM3S9D96.icf</file>
<file>$PROJ_DIR$\Debug\Obj\asm.o</file>
<file>$PROJ_DIR$\Debug\List\ACE32.map</file>
<file>$PROJ_DIR$\asm.s</file>
<file>$PROJ_DIR$\Debug\Exe\ACE32.out</file>
</outputs>
<file>
<name>$PROJ_DIR$\asm.s</name>
<outputs>
<tool>
<name>AARM</name>
<file> 1</file>
</tool>
</outputs>
</file>
<file>
<name>$PROJ_DIR$\Debug\Exe\ACE32.out</name>
<outputs>
<tool>
<name>ILINK</name>
<file> 2</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ILINK</name>
<file> 0 1</file>
</tool>
</inputs>
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<file>
<name>[ROOT_NODE]</name>
<outputs>
<tool>
<name>ILINK</name>
<file> 2 4</file>
</tool>
</outputs>
</file>
</configuration>
<configuration>
<name>Release</name>
<outputs />
<forcedrebuild>
<name>[MULTI_TOOL]</name>
<tool>ILINK</tool>
</forcedrebuild>
</configuration>
</project>
This source diff could not be displayed because it is too large. You can view the blob instead.
This source diff could not be displayed because it is too large. You can view the blob instead.
<?xml version="1.0" encoding="UTF-8"?>
<workspace>
<project>
<path>$WS_DIR$\ACE32.ewp</path>
</project>
<batchBuild />
</workspace>
param([String]$debugfile = "");
# This powershell file has been generated by the IAR Embedded Workbench
# C - SPY Debugger, as an aid to preparing a command line for running
# the cspybat command line utility using the appropriate settings.
#
# Note that this file is generated every time a new debug session
# is initialized, so you may want to move or rename the file before
# making changes.
#
# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed
# by the name of the debug file (usually an ELF / DWARF or UBROF file).
#
# Read about available command line parameters in the C - SPY Debugging
# Guide. Hints about additional command line parameters that may be
# useful in specific cases :
# --download_only Downloads a code image without starting a debug
# session afterwards.
# --silent Omits the sign - on message.
# --timeout Limits the maximum allowed execution time.
#
if ($debugfile -eq "")
{
& "D:\Program Files (x86)\IAR Systems\Embedded Workbench 8.1\common\bin\cspybat" -f "E:\Dropbox2018A\Dropbox\sLi\CCCCCC\Bit32C\ACE_32\ACE32AE1024, (2, 16)\settings\ACE32.Debug.general.xcl" --backend -f "E:\Dropbox2018A\Dropbox\sLi\CCCCCC\Bit32C\ACE_32\ACE32AE1024, (2, 16)\settings\ACE32.Debug.driver.xcl"
}
else
{
& "D:\Program Files (x86)\IAR Systems\Embedded Workbench 8.1\common\bin\cspybat" -f "E:\Dropbox2018A\Dropbox\sLi\CCCCCC\Bit32C\ACE_32\ACE32AE1024, (2, 16)\settings\ACE32.Debug.general.xcl" --debug_file=$debugfile --backend -f "E:\Dropbox2018A\Dropbox\sLi\CCCCCC\Bit32C\ACE_32\ACE32AE1024, (2, 16)\settings\ACE32.Debug.driver.xcl"
}
"--endian=little"
"--cpu=Cortex-M3"
"--fpu=None"
"-p"
"D:\Program Files (x86)\IAR Systems\Embedded Workbench 8.1\arm\CONFIG\debugger\TexasInstruments\LM3S9D96.ddf"
"--semihosting"
"--device=LM3S9D96"
"--multicore_nr_of_cores=1"
"D:\Program Files (x86)\IAR Systems\Embedded Workbench 8.1\arm\bin\armproc.dll"
"D:\Program Files (x86)\IAR Systems\Embedded Workbench 8.1\arm\bin\armsim2.dll"
"E:\Dropbox2018A\Dropbox\sLi\CCCCCC\Bit32C\ACE_32\ACE32AE1024, (2, 16)\Debug\Exe\ACE32.out"
--plugin="D:\Program Files (x86)\IAR Systems\Embedded Workbench 8.1\arm\bin\armbat.dll"
--device_macro="D:\Program Files (x86)\IAR Systems\Embedded Workbench 8.1\arm\config\debugger\TexasInstruments\LM3S.dmac"
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<DataLog>
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<ShowTimeSum>1</ShowTimeSum>
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<DisassembleMode>
<mode>0</mode>
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<Breakpoints2>
<Bp0>_ 0 "STD_CODE2" "{$PROJ_DIR$\asm.s}.18.1" 0 0 1 "" 0 ""</Bp0>
<Bp1>_ 1 "STD_CODE2" "{$PROJ_DIR$\asm.s}.23.1" 0 0 1 "" 0 ""</Bp1>
<Bp2>_ 1 "STD_CODE2" "{$PROJ_DIR$\asm.s}.259.1" 0 0 1 "" 0 ""</Bp2>
<Bp3>_ 1 "STD_CODE2" "{$PROJ_DIR$\asm.s}.259.1" 0 0 1 "" 0 ""</Bp3>
<Count>4</Count>
</Breakpoints2>
<Interrupts>
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<MemConfig>
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<Stop>1</Stop>
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<Aliases>
<Count>0</Count>
<SuppressDialog>0</SuppressDialog>
</Aliases>
<Simulator>
<Freq>10000000</Freq>
<FreqHi>0</FreqHi>
<MultiCoreRunAll>1</MultiCoreRunAll>
</Simulator>
</settings>
<?xml version="1.0" encoding="UTF-8"?>
<project>
<fileVersion>4</fileVersion>
<fileChecksum>2113677428</fileChecksum>
<configuration>
<name>Debug</name>
<outputs>
<file>$PROJ_DIR$\asm.s</file>
<file>$TOOLKIT_DIR$\config\linker\TexasInstruments\LM3S9D96.icf</file>
<file>$PROJ_DIR$\Debug\List\ACE32.map</file>
<file>$PROJ_DIR$\Debug\Obj\asm.o</file>
<file>$PROJ_DIR$\Debug\Exe\ACE32.out</file>
</outputs>
<file>
<name>[ROOT_NODE]</name>
<outputs>
<tool>
<name>ILINK</name>
<file> 4 2</file>
</tool>
</outputs>
</file>
<file>
<name>$PROJ_DIR$\asm.s</name>
<outputs>
<tool>
<name>AARM</name>
<file> 3</file>
</tool>
</outputs>
</file>
<file>
<name>$PROJ_DIR$\Debug\Exe\ACE32.out</name>
<outputs>
<tool>
<name>ILINK</name>
<file> 2</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ILINK</name>
<file> 1 3</file>
</tool>
</inputs>
</file>
</configuration>
<configuration>
<name>Release</name>
<outputs />
<forcedrebuild>
<name>[MULTI_TOOL]</name>
<tool>ILINK</tool>
</forcedrebuild>
</configuration>
</project>
This source diff could not be displayed because it is too large. You can view the blob instead.
This source diff could not be displayed because it is too large. You can view the blob instead.
<?xml version="1.0" encoding="UTF-8"?>
<workspace>
<project>
<path>$WS_DIR$\ACE32.ewp</path>
</project>
<batchBuild />
</workspace>
param([String]$debugfile = "");
# This powershell file has been generated by the IAR Embedded Workbench
# C - SPY Debugger, as an aid to preparing a command line for running
# the cspybat command line utility using the appropriate settings.
#
# Note that this file is generated every time a new debug session
# is initialized, so you may want to move or rename the file before
# making changes.
#
# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed
# by the name of the debug file (usually an ELF / DWARF or UBROF file).
#
# Read about available command line parameters in the C - SPY Debugging
# Guide. Hints about additional command line parameters that may be
# useful in specific cases :
# --download_only Downloads a code image without starting a debug
# session afterwards.
# --silent Omits the sign - on message.
# --timeout Limits the maximum allowed execution time.
#
if ($debugfile -eq "")
{
& "D:\Program Files (x86)\IAR Systems\Embedded Workbench 8.1\common\bin\cspybat" -f "E:\Dropbox2018A\Dropbox\sLi\CCCCCC\Bit32C\ACE_32\ACE_perm_32\settings\ACE32.Debug.general.xcl" --backend -f "E:\Dropbox2018A\Dropbox\sLi\CCCCCC\Bit32C\ACE_32\ACE_perm_32\settings\ACE32.Debug.driver.xcl"
}
else
{
& "D:\Program Files (x86)\IAR Systems\Embedded Workbench 8.1\common\bin\cspybat" -f "E:\Dropbox2018A\Dropbox\sLi\CCCCCC\Bit32C\ACE_32\ACE_perm_32\settings\ACE32.Debug.general.xcl" --debug_file=$debugfile --backend -f "E:\Dropbox2018A\Dropbox\sLi\CCCCCC\Bit32C\ACE_32\ACE_perm_32\settings\ACE32.Debug.driver.xcl"
}
"--endian=little"
"--cpu=Cortex-M3"
"--fpu=None"
"-p"
"D:\Program Files (x86)\IAR Systems\Embedded Workbench 8.1\arm\CONFIG\debugger\TexasInstruments\LM3S9D96.ddf"
"--semihosting"
"--device=LM3S9D96"
"--multicore_nr_of_cores=1"
"D:\Program Files (x86)\IAR Systems\Embedded Workbench 8.1\arm\bin\armproc.dll"
"D:\Program Files (x86)\IAR Systems\Embedded Workbench 8.1\arm\bin\armsim2.dll"
"E:\Dropbox2018A\Dropbox\sLi\CCCCCC\Bit32C\ACE_32\ACE_perm_32\Debug\Exe\ACE32.out"
--plugin="D:\Program Files (x86)\IAR Systems\Embedded Workbench 8.1\arm\bin\armbat.dll"
--device_macro="D:\Program Files (x86)\IAR Systems\Embedded Workbench 8.1\arm\config\debugger\TexasInstruments\LM3S.dmac"
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<TriggerName>main</TriggerName>
<LimitSize>0</LimitSize>
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<ShowTimeLog>1</ShowTimeLog>
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<ShowTimeSum>1</ShowTimeSum>
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<DisassembleMode>
<mode>0</mode>
</DisassembleMode>
<Breakpoints2>
<Bp0>_ 1 "STD_CODE2" "{$PROJ_DIR$\asm.s}.259.1" 0 0 1 "" 0 ""</Bp0>
<Bp1>_ 1 "STD_CODE2" "{$PROJ_DIR$\asm.s}.259.1" 0 0 1 "" 0 ""</Bp1>
<Count>2</Count>
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<Interrupts>
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<Freq>10000000</Freq>
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</settings>
......@@ -17,11 +17,19 @@
#define NUMSTEPS 16
#define PARAL_INST_BY4 1
//New
/*
*SC0: step constants, applied on B
*SC1: step constants, applied on D
*SC2: step constants, applied on E
*/
static const unsigned char SC0[16]={0x50,0x5c,0x91,0x8d,0x53,0x60,0x68,0xe1,0xf6,0x9d,0x40,0x4f,0xbe,0x5b,0xe9,0x7f}; //Step constants (SC_{2i})
static const unsigned char SC1[16]={0x28,0xae,0x48,0xc6,0xa9,0x30,0x34,0x70,0x7b,0xce,0x20,0x27,0x5f,0xad,0x74,0x3f}; //Step constants (SC_{2i+1})
static const unsigned char SC2[16]={0x14,0x57,0x24,0x63,0x54,0x18,0x9a,0x38,0xbd,0x67,0x10,0x13,0x2f,0xd6,0xba,0x1f}; //Step constants (SC_{2i+2})
/*
*RC0: round constants of simeck box applied on A
*RC1: round constants of simeck box applied on C
*RC2: round constants of simeck box applied on E
*/
static const unsigned char RC0[16]={0x07,0x0a,0x9b,0xe0,0xd1,0x1a,0x22,0xf7,0x62,0x96,0x71,0xaa,0x2b,0xe9,0xcf,0xb7};//Round constants (RC_{2i})
static const unsigned char RC1[16]={0x53,0x5d,0x49,0x7f,0xbe,0x1d,0x28,0x6c,0x82,0x47,0x6b,0x88,0xdc,0x8b,0x59,0xc6};//Round constants (RC_{2i+1})
static const unsigned char RC2[16]={0x43,0xe4,0x5e,0xcc,0x32,0x4e,0x75,0x25,0xfd,0xf9,0x76,0xa0,0xb0,0x09,0x1e,0xad};//Round constants (RC_{2i+2})
......
/* Reference implementation of ACE-128, AEAD
Written by:
Kalikinkar Mandal <kmandal@uwaterloo.ca>
Currently this implementation supports aead computation
when input message length is a multiple of 64 bits.
*/
#include<stdio.h>
......@@ -34,7 +37,7 @@ int main()
u32 *state;
int i, j;
u64 t[NUM_ITER+1], count_cc;
u64 count_cc;
u32 *plaintext, *ciphertext, *tag, *key, *nonce, *ad;
u32 plen, tlen, klen, adlen;
......@@ -63,7 +66,7 @@ int main()
//Randomly initilizes messages to states
for ( i = 0; i < num_parallel_inst*STATEDWORD; i++ )
*(state+i) = i%STATEDWORD;
//*(state+i) = 0x01;
//*(state+i) = 0x0;
print_state(state);
ace320( state );
......@@ -74,8 +77,10 @@ int main()
//Assinging 128-bit keys, nonces and messages//
for ( i = 0; i < num_parallel_inst*klen; i++ )
{
*(nonce+i) = 0x40404040;
*(key+i) = 0x10101010;
//*(nonce+i) = 0x40404040;
//*(key+i) = 0x10101010;
*(nonce+i) = 0x0;
*(key+i) = 0x0;
}
for ( i = 0; i < num_parallel_inst; i++ )
{
......
......@@ -8,14 +8,15 @@
-- Kalikinkar Mandal
-- Raghvendra Rohit
-- Marat Sattarov
-- http://comsec.uwaterloo.ca
-- Nusa Zidaric
-- http://uwaterloo.ca/communications-security-lab/lwc/ace
-- This is a human-readable summary of (and not a substitute for) the license.
-- You are free to:
-- Share copy and redistribute the material in any medium or format
-- Adapt remix, transform, and build upon the material
-- Share: copy and redistribute the material in any medium or format
-- Adapt: remix, transform, and build upon the material
-- The licensor cannot revoke these freedoms as long as you follow
-- the license terms.
......
LIB_VHDL =+ ace_pkg.vhd
TB_ENTITY = ace_tb
TB_ARCH = main
TB_VHDL =+ util_unsynth.vhd
TB_VHDL =+ ace_unsynth.vhd
TB_VHDL =+ ace_tb.vhd
SIM_SCRIPT = ace_tb.sim
DESIGN_ARCH = rtl
DESIGN_ENTITY = ace
DESIGN_VHDL =+ sb_64.vhd
DESIGN_VHDL =+ lfsr_c.vhd
DESIGN_VHDL =+ ctl.vhd
DESIGN_VHDL =+ dp.vhd
ENTITY_VHDL =+ ace.vhd
DESIGN_VHDL =+ ace-rtl.vhd
......@@ -8,14 +8,15 @@
-- Kalikinkar Mandal
-- Raghvendra Rohit
-- Marat Sattarov
-- http://comsec.uwaterloo.ca
-- Nusa Zidaric
-- http://uwaterloo.ca/communications-security-lab/lwc/ace
-- This is a human-readable summary of (and not a substitute for) the license.
-- You are free to:
-- Share copy and redistribute the material in any medium or format
-- Adapt remix, transform, and build upon the material
-- Share: copy and redistribute the material in any medium or format
-- Adapt: remix, transform, and build upon the material
-- The licensor cannot revoke these freedoms as long as you follow
-- the license terms.
......
......@@ -8,14 +8,15 @@
-- Kalikinkar Mandal
-- Raghvendra Rohit
-- Marat Sattarov
-- http://comsec.uwaterloo.ca
-- Nusa Zidaric
-- http://uwaterloo.ca/communications-security-lab/lwc/ace
-- This is a human-readable summary of (and not a substitute for) the license.
-- You are free to:
-- Share copy and redistribute the material in any medium or format
-- Adapt remix, transform, and build upon the material
-- Share: copy and redistribute the material in any medium or format
-- Adapt: remix, transform, and build upon the material
-- The licensor cannot revoke these freedoms as long as you follow
-- the license terms.
......
......@@ -56,7 +56,7 @@ if { $gui_mode } {
}
vcd file ace.vcd
vcd file uw_tmp/ace.vcd
vcd add /ace_tb/uut/*
vcd add -r *
......
......@@ -8,14 +8,15 @@
-- Kalikinkar Mandal
-- Raghvendra Rohit
-- Marat Sattarov
-- http://comsec.uwaterloo.ca
-- Nusa Zidaric
-- http://uwaterloo.ca/communications-security-lab/lwc/ace
-- This is a human-readable summary of (and not a substitute for) the license.
-- You are free to:
-- Share copy and redistribute the material in any medium or format
-- Adapt remix, transform, and build upon the material
-- Share: copy and redistribute the material in any medium or format
-- Adapt: remix, transform, and build upon the material
-- The licensor cannot revoke these freedoms as long as you follow
-- the license terms.
......@@ -58,14 +59,14 @@ use work.ace_pkg.all;
--use work.wg_config_pkg.all;
entity ace_tb is
generic (
period : real --:= 10.0
);
generic ( period : real --:= 10.0
; EDH : std_logic_vector(0 to 2) := "111" -- ENCRYPTION, DECRYPTION, HASH bits. example: 'xx0' = don't do HASH, 'xx1' = do HASH
);
end entity;
architecture main of ace_tb is
constant EDH : std_logic_vector(0 to 2) := "111"; -- ENCRYPTION / DECRYPTION / HASH: '0' = don't do, '1' = do
--constant EDH : std_logic_vector(0 to 2) := "100"; -- ENCRYPTION, DECRYPTION, HASH bits. example: 'xx0' = don't do HASH, 'xx1' = do HASH
constant stim_file_path : string := "dp_tv/nist_test.tv";
constant output_file_path : string := "dp_tv/output.tv";
......@@ -74,7 +75,7 @@ architecture main of ace_tb is
constant clk_period : time := period * 1 ns;
constant hold : time := clk_period / 2;
constant hold : time := clk_period / 10;
constant after_reset : time := 0 * clk_period; -- delay between reset and loading
constant load_delay : time := 0 * clk_period; -- delay between K, N data
constant init_delay : time := 0 * clk_period; -- delay between load permutation and initialization
......@@ -88,11 +89,13 @@ architecture main of ace_tb is
signal reset : std_logic := '0';
signal i_mode : mode_ty;
signal i_mode_buf : mode_ty;
signal ctl_control : ace_ctl_ty;
signal ctl_onehot : onehot_ty;
signal i_const : lfsr_c_output;
signal i_dom_sep : domsep_ty;
signal i_dom_sep_buf : domsep_ty;
signal i_valid : std_logic := '0';
signal i_data : word;
signal ctl_count : count_ty;
......@@ -111,6 +114,16 @@ architecture main of ace_tb is
begin
i_dom_sep_proc : process(i_dom_sep_buf)
begin
i_dom_sep <= i_dom_sep_buf after hold;
end process;
i_mode_proc : process(i_mode_buf)
begin
i_mode <= i_mode_buf after hold;
end process;
uut : entity work.ace port map
( clk => clk
, reset => reset
......@@ -171,7 +184,7 @@ begin
------------------------- SIGNAL DEFAULTS ----------------------------
i_padding <= '0';
i_data <= (others => 'X');
i_dom_sep <= (others => 'X');
i_dom_sep_buf <= (others => 'X');
tb_state <= tbNull;
if EDH(0) = '1' then
......@@ -196,10 +209,10 @@ begin
n0 := nonce_stim(0 to word_sz - 1);
n1 := nonce_stim(word_sz to key_sz - 1);
i_mode <= encrypt_mode;
i_mode_buf <= encrypt_mode;
wait for hold;
drive_data( clk, k0, hold, i_data, i_valid ); wait for load_delay;
drive_data( clk, k1, hold, i_data, i_valid ); wait for load_delay;
drive_data( clk, n0, hold, i_data, i_valid ); wait for load_delay;
......@@ -213,17 +226,20 @@ begin
---------------------------------- Init --------------------------------
report( "INITIALIZATION PHASE" );
i_dom_sep <= "00";
i_dom_sep_buf <= "00";
drive_data( clk, k0, hold, i_data, i_valid );
wait until o_ready = '1' and rising_edge(clk);
drive_data( clk, k1, hold, i_data, i_valid );
wait until o_ready = '1' and rising_edge(clk);
---------------------------------- ProcAD --------------------------------
report( "AD PROCESSING PHASE" );
i_dom_sep <= "01";
i_dom_sep_buf <= "01";
drive_all(AD_TAG, stim_file_path, hold, procad_delay, false, clk, o_ready, o_data, i_data, i_valid, i_padding, bits_pad);
---------------------------------- Encrypt ------------------------------
......@@ -231,15 +247,18 @@ begin
tb_state <= tbEncrypt;
i_dom_sep <= "10";
i_dom_sep_buf <= "10";
drive_all(PLAINTEXT_TAG, stim_file_path, hold, enc_delay, false, clk, o_ready, o_data, i_data, i_valid, i_padding, bits_pad);
---------------------------------- Final --------------------------------
report( "FINALIZATION PHASE" );
i_dom_sep <= "00";
i_dom_sep_buf <= "00";
drive_data( clk, k0, hold, i_data, i_valid );
wait until o_ready = '1' and rising_edge(clk);
drive_data( clk, k1, hold, i_data, i_valid );
---------------------------------- Tag ----------------------------------
......@@ -262,7 +281,7 @@ begin
------------------------- SIGNAL DEFAULTS ----------------------------
i_data <= (others => 'X');
i_dom_sep <= (others => 'X');
i_dom_sep_buf <= (others => 'X');
------------------------ READING STIM FILES -------------------------
......@@ -282,9 +301,9 @@ begin
n0 := nonce_stim(0 to word_sz - 1);
n1 := nonce_stim(word_sz to key_sz - 1);
i_mode <= decrypt_mode;
i_mode_buf <= decrypt_mode;
wait for hold;
drive_data( clk, k0, hold, i_data, i_valid ); wait for load_delay;
drive_data( clk, k1, hold, i_data, i_valid ); wait for load_delay;
drive_data( clk, n0, hold, i_data, i_valid ); wait for load_delay;
......@@ -300,10 +319,12 @@ begin
report( "INITIALIZATION PHASE" );
i_dom_sep <= "00";
i_dom_sep_buf <= "00";
drive_data( clk, k0, hold, i_data, i_valid );
wait until o_ready = '1' and rising_edge(clk);
drive_data( clk, k1, hold, i_data, i_valid );
wait until o_ready = '1' and rising_edge(clk);
......@@ -311,7 +332,8 @@ begin
report( "AD PROCESSING PHASE" );
i_dom_sep <= "01";
i_dom_sep_buf <= "01";
drive_all(AD_TAG, stim_file_path, hold, procad_delay, false, clk, o_ready, o_data, i_data, i_valid, i_padding, bits_pad);
......@@ -321,16 +343,19 @@ begin
tb_state <= tbDecrypt;
i_dom_sep <= "10";
i_dom_sep_buf <= "10";
drive_all(CIPHERTEXT_TAG, stim_file_path, hold, enc_delay, true, clk, o_ready, o_data, i_data, i_valid, i_padding, bits_pad);
---------------------------------- Final --------------------------------
report( "FINALIZATION PHASE" );
i_dom_sep <= "00";
i_dom_sep_buf <= "00";
drive_data( clk, k0, hold, i_data, i_valid );
wait until o_ready = '1' and rising_edge(clk);
drive_data( clk, k1, hold, i_data, i_valid );
---------------------------------- Tag ----------------------------------
......@@ -355,7 +380,7 @@ begin
------------------------- SIGNAL DEFAULTS ----------------------------
i_data <= (others => 'X');
i_dom_sep <= (others => 'X');
i_dom_sep_buf <= (others => 'X');
------------------------ READING STIM FILES -------------------------
iv := x"8040400000000000";
......@@ -367,9 +392,8 @@ begin
-------------------------------- Load --------------------------------
report( "LOADING PHASE" );
i_mode <= absorb_mode;
i_mode_buf <= absorb_mode;
wait for hold;
drive_data( clk, iv, hold, i_data, i_valid ); wait for load_delay;
-------------------------------- LoadPerm ------------------------------
......@@ -379,15 +403,17 @@ begin
--------------------------------- Absorb -------------------------------
i_dom_sep <= "00";
i_dom_sep_buf <= "00";
report( "HASH DRIVE ALL" );
drive_all(PLAINTEXT_TAG, stim_file_path, hold, enc_delay, false, clk, o_ready, o_data, i_data, i_valid, i_padding, bits_pad);
--------------------------------- Squeeze -------------------------------
wait for hold;
tb_state <= tbHash;
i_mode <= squeeze_mode;
i_mode_buf <= squeeze_mode;
end if;
......
**** Line 63 (old) / 63 (new) ****
Description:
Moved EDH to the list of generics
Change:
; EDH : std_logic_vector(0 to 2) := "111" -- ENCRYPTION, DECRYPTION, HASH bits. example: 'xx0' = don't do HASH, 'xx1' = do HASH
**** Line 68 (old) / 69 (new) ****
Description:
Removed EDH signal declaration
**** Line 91,96 (old) / 92,98 (new) ****
Description:
Added new signal declarations to delay primary inputs after clock edge
Change:
signal i_mode_buf : mode_ty;
signal i_dom_sep_buf : domsep_ty;
**** Line 114 (old) / 117 - 125 (new) ****
Description:
added new processes to delay a change in primary inputs after clock edge
Change:
i_dom_sep_proc : process(i_dom_sep_buf)
begin
i_dom_sep <= i_dom_sep_buf after hold;
end process;
i_mode_proc : process(i_mode_buf)
begin
i_mode <= i_mode_buf after hold;
end process;
**** Line 199 (old) / 212 (new) ****
**** Line 285 (old) / 304 (new) ****
**** Line 370 (old) / 395 (new) ****
**** Line 390 (old) / 416 (new) ****
Description:
changed signal name
Change:
was
i_mode
now
i_mode_buf
**** Line 216 (old) / 229 (new) ****
**** Line 226 (old) / 241 (new) ****
**** Line 234 (old) / 250 (new) ****
**** Line 239 (old) / 256 (new) ****
**** Line 265 (old) / 284 (new) ****
**** Line 303 (old) / 322 (new) ****
**** Line 314 (old) / 335 (new) ****
**** Line 324 (old) / 346 (new) ****
**** Line 330 (old) / 353 (new) ****
**** Line 358 (old) / 383 (new) ****
**** Line 382 (old) / 406 (new) ****
Description:
changed signal name
Change:
was
i_dom_sep
now
i_dom_sep_buf
**** Line 202 (old) / 215 (new) ****
**** Line 287 (old) / 306 (new) ****
**** Line 372 (old) / 396 (new) ****
**** Line 387 (old) / 413 (new) ****
Description:
Hold statements are now in ace_unsynth.vhd
Change:
removed
wait for hold;
**** Line 383 (old) / 407 (new) ****
Description
Added a report
Change:
report( "HASH DRIVE ALL" );
......@@ -8,14 +8,15 @@
-- Kalikinkar Mandal
-- Raghvendra Rohit
-- Marat Sattarov
-- http://comsec.uwaterloo.ca
-- Nusa Zidaric
-- http://uwaterloo.ca/communications-security-lab/lwc/ace
-- This is a human-readable summary of (and not a substitute for) the license.
-- You are free to:
-- Share copy and redistribute the material in any medium or format
-- Adapt remix, transform, and build upon the material
-- Share: copy and redistribute the material in any medium or format
-- Adapt: remix, transform, and build upon the material
-- The licensor cannot revoke these freedoms as long as you follow
-- the license terms.
......@@ -128,6 +129,7 @@ package body ace_unsynth is
is
begin
wait for hold;
i_data <= data;
i_valid <= '1';
wait until rising_edge(clk);
......@@ -160,7 +162,7 @@ package body ace_unsynth is
begin
break := false;
i_padding <= '0';
i_padding <= '0';--
num_bits_pad := 64;
bits_pad <= 64;
......@@ -195,6 +197,7 @@ package body ace_unsynth is
end if;
if break then
wait for hold;
i_data <= data; -- ciphertext goes here
i_valid <= '1';
i_padding <= '1'; ---- handle the padding
......@@ -224,6 +227,7 @@ package body ace_unsynth is
bits_pad <= num_bits - 64;
if break then
wait for hold;
i_data <= data; -- ciphertext goes here
i_valid <= '1';
i_padding <= '1'; ---- handle the padding
......
**** Line 130 (old), 132 (new) ****
**** Line 198 (old), 200 (new) ****
**** Line 227 (old), 230 (new) ****
Description:
added a hold statement to delay primary inputs from clock edge
Change:
wait for hold;
......@@ -8,14 +8,15 @@
-- Kalikinkar Mandal
-- Raghvendra Rohit
-- Marat Sattarov
-- http://comsec.uwaterloo.ca
-- Nusa Zidaric
-- http://uwaterloo.ca/communications-security-lab/lwc/ace
-- This is a human-readable summary of (and not a substitute for) the license.
-- You are free to:
-- Share copy and redistribute the material in any medium or format
-- Adapt remix, transform, and build upon the material
-- Share: copy and redistribute the material in any medium or format
-- Adapt: remix, transform, and build upon the material
-- The licensor cannot revoke these freedoms as long as you follow
-- the license terms.
......
......@@ -8,14 +8,15 @@
-- Kalikinkar Mandal
-- Raghvendra Rohit
-- Marat Sattarov
-- http://comsec.uwaterloo.ca
-- Nusa Zidaric
-- http://uwaterloo.ca/communications-security-lab/lwc/ace
-- This is a human-readable summary of (and not a substitute for) the license.
-- You are free to:
-- Share copy and redistribute the material in any medium or format
-- Adapt remix, transform, and build upon the material
-- Share: copy and redistribute the material in any medium or format
-- Adapt: remix, transform, and build upon the material
-- The licensor cannot revoke these freedoms as long as you follow
-- the license terms.
......
-- This work is licensed under a Creative Commons
-- Attribution-NonCommercial-ShareAlike 4.0 International License.
-- http://creativecommons.org/licenses/by-nc-sa/4.0
-- Mark D. Aagaard
-- Riham AlTawy
-- Guang Gong
-- Kalikinkar Mandal
-- Raghvendra Rohit
-- Marat Sattarov
-- http://comsec.uwaterloo.ca
-- This is a human-readable summary of (and not a substitute for) the license.
-- You are free to:
-- Share — copy and redistribute the material in any medium or format
-- Adapt — remix, transform, and build upon the material
-- The licensor cannot revoke these freedoms as long as you follow
-- the license terms.
-- Under the following terms:
-- Attribution — You must give appropriate credit, provide a link to
-- the license, and indicate if changes were made. You may do so in
-- any reasonable manner, but not in any way that suggests the
-- licensor endorses you or your use.
-- NonCommercial — You may not use the material for commercial
-- purposes.
-- ShareAlike — If you remix, transform, or build upon the material,
-- you must distribute your contributions under the same license as
-- the original.
-- No additional restrictions — You may not apply legal terms or
-- technological measures that legally restrict others from doing
-- anything the license permits.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ace_pkg.all;
entity dp is
port
( clk : in std_logic
; reset : in std_logic
; i_mode : in mode_ty
; i_control : in ace_ctl_ty
; i_onehot : in onehot_ty
; i_dom_sep : in domsep_ty
; i_valid : in std_logic
; i_data : in word
; i_padding : in std_logic
; o_data : out word
);
end entity;
architecture rtl of dp is
signal permoff, endstep, squeeze,
absorb, replace, output,
lfsr_reset, lfsr_en : std_logic;
signal ace_state, post_input : half_word_state_ty;
signal pre_round, post_round,
post_xor, post_step_const,
post_linear, ace_path : word_state_ty;
signal dsxor : half_word;
signal i_data_vector, o_data_vector : half_word_data;
signal ctl_const : lfsr_c_output;
begin
u_lfsr :
entity work.lfsr port map
( clk => clk
, reset => lfsr_reset
, lfsr_en => lfsr_en
, o_const => ctl_const
);
i_data_vector <= data_to_vector( i_data );
o_data <= vector_to_data( o_data_vector );
absorb <= i_control( absorb_idx );
replace <= i_control( replace_idx );
output <= i_control( output_idx );
endstep <= i_control( endstep_idx );
permoff <= i_control( permoff_idx );
squeeze <= i_control( squeeze_idx );
lfsr_reset <= i_control( lfsr_reset_idx );
lfsr_en <= i_control( lfsr_en_idx );
----------------------------------------------------------------------
-- post input: do input and domain separator and replace
post_input( a1_idx ) <= ace_state( a1_idx );
post_input( a0_idx ) <= ace_state( a0_idx );
post_input( b0_idx ) <= ace_state( b0_idx );
post_input( b1_idx ) <= ace_state( b1_idx );
post_input( c0_idx ) <= ace_state( c0_idx );
post_input( c1_idx ) <= ace_state( c1_idx );
post_input( d0_idx ) <= ace_state( d0_idx );
post_input( d1_idx ) <= ace_state( d1_idx );
post_input( e1_idx ) <= ace_state( e1_idx );
dsxor( 0 to half_word_sz - 3 ) <= ( others => '0' );
dsxor( half_word_sz - 2) <= i_dom_sep(1);
dsxor( half_word_sz - 1) <= i_dom_sep(0);
post_input( e0_idx ) <= dsxor xor ace_state( e0_idx ) when (i_valid = '1')
else ace_state( e0_idx );
----------------------------------------------------------------------
o_data_vector(0) <= ace_state(a1_idx);
---------------------------------------------------------------------
-- sb 64 ==> post round
pre_round <= half_words_to_words( post_input );
a_sb_64 :
entity work.sb_64 port map
( i_state => pre_round( a_idx )
, i_rc => ctl_const( lfsr_c_sz + 2 ) --rc0
, o_state => post_round( a_idx )
);
post_round( b_idx ) <= pre_round( b_idx );
c_sb_64 :
entity work.sb_64 port map
( i_state => pre_round( c_idx )
, i_rc => ctl_const( lfsr_c_sz + 1 ) --rc1
, o_state => post_round( c_idx )
);
post_round( d_idx ) <= pre_round( d_idx );
e_sb_64 :
entity work.sb_64 port map
( i_state => pre_round( e_idx )
, i_rc => ctl_const( lfsr_c_sz ) -- rc2
, o_state => post_round( e_idx )
);
----------------------------------------------------------------------
-- XORs to the left ==> post xor
post_xor( a_idx ) <= post_round( a_idx );
post_xor( c_idx ) <= post_round( c_idx );
post_xor( b_idx ) <= post_round( b_idx ) xor post_round( c_idx );
post_xor( d_idx ) <= post_round( d_idx ) xor post_round( e_idx );
post_xor( e_idx ) <= post_round( e_idx ) xor post_round( a_idx );
----------------------------------------------------------------------
-- XOR with step constant ==> post step const
post_step_const( a_idx ) <= post_xor( a_idx );
post_step_const( c_idx ) <= post_xor( c_idx );
post_step_const( b_idx)( 0 to 55) <= not post_xor( b_idx )( 0 to 55 );
post_step_const( b_idx)( 56 to 63) <= post_xor( b_idx )( 56 to 63 ) xor ctl_const( 2 to lfsr_c_sz + 2 ); -- sc0
post_step_const( d_idx)( 0 to 55) <= not post_xor( d_idx )( 0 to 55 );
post_step_const( d_idx)( 56 to 63) <= post_xor( d_idx )( 56 to 63 ) xor ctl_const( 1 to lfsr_c_sz + 1 ); -- sc1
post_step_const( e_idx)( 0 to 55) <= not post_xor( e_idx )( 0 to 55 );
post_step_const( e_idx)( 56 to 63) <= post_xor( e_idx )( 56 to 63 ) xor ctl_const( 0 to lfsr_c_sz ); --sc2
------------------------------------------------------------
-- post liear layer pi = (3,2,0,4,1) ==> post linear
post_linear( a_idx ) <= post_step_const( d_idx );
post_linear( b_idx ) <= post_step_const( c_idx );
post_linear( c_idx ) <= post_step_const( a_idx );
post_linear( d_idx ) <= post_step_const( e_idx );
post_linear( e_idx ) <= post_step_const( b_idx );
------------------------------------------------------------
-- update state
ace_path( a_idx ) <= post_linear( a_idx ) when endstep = '1' else post_round( a_idx );
ace_path( b_idx ) <= post_linear( b_idx ) when endstep = '1' else post_round( b_idx );
ace_path( c_idx ) <= post_linear( c_idx ) when endstep = '1' else post_round( c_idx );
ace_path( d_idx ) <= post_linear( d_idx ) when endstep = '1' else post_round( d_idx );
ace_path( e_idx ) <= post_linear( e_idx ) when endstep = '1' else post_round( e_idx );
process
begin
wait until rising_edge( clk );
ace_state <= words_to_half_words(ace_path);
end process;
end architecture;
The file dp_pure.vhd was removed from the submission, because it is not part of the functional complete cipher.
......@@ -8,14 +8,15 @@
-- Kalikinkar Mandal
-- Raghvendra Rohit
-- Marat Sattarov
-- http://comsec.uwaterloo.ca
-- Nusa Zidaric
-- http://uwaterloo.ca/communications-security-lab/lwc/ace
-- This is a human-readable summary of (and not a substitute for) the license.
-- You are free to:
-- Share copy and redistribute the material in any medium or format
-- Adapt remix, transform, and build upon the material
-- Share: copy and redistribute the material in any medium or format
-- Adapt: remix, transform, and build upon the material
-- The licensor cannot revoke these freedoms as long as you follow
-- the license terms.
......
......@@ -8,14 +8,15 @@
-- Kalikinkar Mandal
-- Raghvendra Rohit
-- Marat Sattarov
-- http://comsec.uwaterloo.ca
-- Nusa Zidaric
-- http://uwaterloo.ca/communications-security-lab/lwc/ace
-- This is a human-readable summary of (and not a substitute for) the license.
-- You are free to:
-- Share copy and redistribute the material in any medium or format
-- Adapt remix, transform, and build upon the material
-- Share: copy and redistribute the material in any medium or format
-- Adapt: remix, transform, and build upon the material
-- The licensor cannot revoke these freedoms as long as you follow
-- the license terms.
......
......@@ -8,14 +8,15 @@
-- Kalikinkar Mandal
-- Raghvendra Rohit
-- Marat Sattarov
-- http://comsec.uwaterloo.ca
-- Nusa Zidaric
-- http://uwaterloo.ca/communications-security-lab/lwc/ace
-- This is a human-readable summary of (and not a substitute for) the license.
-- You are free to:
-- Share copy and redistribute the material in any medium or format
-- Adapt remix, transform, and build upon the material
-- Share: copy and redistribute the material in any medium or format
-- Adapt: remix, transform, and build upon the material
-- The licensor cannot revoke these freedoms as long as you follow
-- the license terms.
......
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