.PHONY: clean

YOSYS_TOOL=yosys

SYNTHESIS_SCRIPT=synth.tcl
SOURCE_SCRIPT=source.tcl

SUBTERRANEAN_SOURCE_FOLDER=../verilog_source
SYNTHESIS_FOLDER_OUTPUT=synth_output

STD_CELL_LIBRARY_FOLDER=/home/pedro/asic_cells
STD_CELL_PIN_CONSTRAINTS_FOLDER=pin_contraints
STD_CELL_TIMING_CONSTRAINT=1
STD_CELL_LIBRARY=gscl45nm

SUBTERRANEAN_ROUND_SOURCE=\
	$(SUBTERRANEAN_SOURCE_FOLDER)/subterranean_round.v

SUBTERRANEAN_ROUND_WITH_COMMUNCATION_SOURCE=\
	$(SUBTERRANEAN_ROUND_SOURCE)\
	$(SUBTERRANEAN_SOURCE_FOLDER)/subterranean_round_with_communication.v\

SUBTERRANEAN_SIMPLE_NO_COMMUNCATION_SOURCE=\
	$(SUBTERRANEAN_ROUND_SOURCE)\
	$(SUBTERRANEAN_SOURCE_FOLDER)/subterranean_simple_no_communication.v

SUBTERRANEAN_SIMPLE_AXI4_LITE_SOURCE=\
	$(SUBTERRANEAN_SIMPLE_NO_COMMUNCATION_SOURCE)\
	$(SUBTERRANEAN_SOURCE_FOLDER)/subterranean_simple_axi4_lite.v

all : subterranean_round subterranean_round_with_communication subterranean_simple_no_communication subterranean_simple_axi4_lite

subterranean_round:
	mkdir -p $(SYNTHESIS_FOLDER_OUTPUT)
	mkdir -p $(SYNTHESIS_FOLDER_OUTPUT)/$(STD_CELL_LIBRARY)
	SYNTH_TOP_UNIT_NAME="$@" SYNTH_ASIC_CELL_LOCATION="$(STD_CELL_LIBRARY_FOLDER)/$(STD_CELL_LIBRARY).lib" SYNTH_ASIC_PIN_CONSTRAINTS="$(STD_CELL_PIN_CONSTRAINTS_FOLDER)/$(STD_CELL_LIBRARY).constr" SYNTH_TIMING_CONSTRAINT="$(STD_CELL_TIMING_CONSTRAINT)" SYNTH_OUTPUT_CIRCUIT_FOLDER="$(SYNTHESIS_FOLDER_OUTPUT)/$(STD_CELL_LIBRARY)/" $(YOSYS_TOOL) -l "$(SYNTHESIS_FOLDER_OUTPUT)/$(STD_CELL_LIBRARY)/$@.yslog" -c $(SYNTHESIS_SCRIPT) -q

subterranean_round_with_communication:
	mkdir -p $(SYNTHESIS_FOLDER_OUTPUT)
	mkdir -p $(SYNTHESIS_FOLDER_OUTPUT)/$(STD_CELL_LIBRARY)
	SYNTH_TOP_UNIT_NAME="$@" SYNTH_ASIC_CELL_LOCATION="$(STD_CELL_LIBRARY_FOLDER)/$(STD_CELL_LIBRARY).lib" SYNTH_ASIC_PIN_CONSTRAINTS="$(STD_CELL_PIN_CONSTRAINTS_FOLDER)/$(STD_CELL_LIBRARY).constr" SYNTH_TIMING_CONSTRAINT="$(STD_CELL_TIMING_CONSTRAINT)" SYNTH_OUTPUT_CIRCUIT_FOLDER="$(SYNTHESIS_FOLDER_OUTPUT)/$(STD_CELL_LIBRARY)/" $(YOSYS_TOOL) -l "$(SYNTHESIS_FOLDER_OUTPUT)/$(STD_CELL_LIBRARY)/$@.yslog" -c $(SYNTHESIS_SCRIPT) -q

subterranean_simple_no_communication:
	mkdir -p $(SYNTHESIS_FOLDER_OUTPUT)
	mkdir -p $(SYNTHESIS_FOLDER_OUTPUT)/$(STD_CELL_LIBRARY)
	SYNTH_TOP_UNIT_NAME="$@" SYNTH_ASIC_CELL_LOCATION="$(STD_CELL_LIBRARY_FOLDER)/$(STD_CELL_LIBRARY).lib" SYNTH_ASIC_PIN_CONSTRAINTS="$(STD_CELL_PIN_CONSTRAINTS_FOLDER)/$(STD_CELL_LIBRARY).constr" SYNTH_TIMING_CONSTRAINT="$(STD_CELL_TIMING_CONSTRAINT)" SYNTH_OUTPUT_CIRCUIT_FOLDER="$(SYNTHESIS_FOLDER_OUTPUT)/$(STD_CELL_LIBRARY)/" $(YOSYS_TOOL) -l "$(SYNTHESIS_FOLDER_OUTPUT)/$(STD_CELL_LIBRARY)/$@.yslog" -c $(SYNTHESIS_SCRIPT) -q

subterranean_simple_axi4_lite:
	mkdir -p $(SYNTHESIS_FOLDER_OUTPUT)
	mkdir -p $(SYNTHESIS_FOLDER_OUTPUT)/$(STD_CELL_LIBRARY)
	SYNTH_TOP_UNIT_NAME="$@" SYNTH_ASIC_CELL_LOCATION="$(STD_CELL_LIBRARY_FOLDER)/$(STD_CELL_LIBRARY).lib" SYNTH_ASIC_PIN_CONSTRAINTS="$(STD_CELL_PIN_CONSTRAINTS_FOLDER)/$(STD_CELL_LIBRARY).constr" SYNTH_TIMING_CONSTRAINT="$(STD_CELL_TIMING_CONSTRAINT)" SYNTH_OUTPUT_CIRCUIT_FOLDER="$(SYNTHESIS_FOLDER_OUTPUT)/$(STD_CELL_LIBRARY)/" $(YOSYS_TOOL) -l "$(SYNTHESIS_FOLDER_OUTPUT)/$(STD_CELL_LIBRARY)/$@.yslog" -c $(SYNTHESIS_SCRIPT) -q

clean:
	@echo "Cleaning up..."
	rm -f $(SYNTHESIS_FOLDER_OUTPUT)/$(STD_CELL_LIBRARY)/*.yslog
	rm -f $(SYNTHESIS_FOLDER_OUTPUT)/$(STD_CELL_LIBRARY)/*.v
	@echo "Cleaning done."