#if defined(__AVR__) #include <avr/io.h> /* Automatically generated - do not edit */ #include "internal-gift128-config.h" #if GIFT128_VARIANT == GIFT128_VARIANT_TINY .section .progmem.data,"a",@progbits .p2align 8 .type table_0, @object .size table_0, 160 table_0: .byte 8 .byte 0 .byte 0 .byte 16 .byte 0 .byte 128 .byte 1 .byte 128 .byte 2 .byte 0 .byte 0 .byte 84 .byte 129 .byte 1 .byte 1 .byte 1 .byte 31 .byte 0 .byte 0 .byte 128 .byte 128 .byte 136 .byte 136 .byte 16 .byte 0 .byte 224 .byte 1 .byte 96 .byte 2 .byte 0 .byte 80 .byte 81 .byte 128 .byte 1 .byte 3 .byte 3 .byte 47 .byte 0 .byte 0 .byte 128 .byte 128 .byte 136 .byte 8 .byte 16 .byte 0 .byte 96 .byte 1 .byte 96 .byte 2 .byte 0 .byte 80 .byte 65 .byte 128 .byte 0 .byte 3 .byte 3 .byte 39 .byte 0 .byte 0 .byte 128 .byte 128 .byte 136 .byte 0 .byte 16 .byte 0 .byte 224 .byte 1 .byte 64 .byte 2 .byte 0 .byte 80 .byte 17 .byte 128 .byte 1 .byte 2 .byte 3 .byte 43 .byte 0 .byte 0 .byte 128 .byte 128 .byte 8 .byte 8 .byte 16 .byte 0 .byte 64 .byte 1 .byte 96 .byte 2 .byte 0 .byte 64 .byte 1 .byte 128 .byte 0 .byte 2 .byte 2 .byte 33 .byte 0 .byte 0 .byte 128 .byte 128 .byte 0 .byte 0 .byte 16 .byte 0 .byte 192 .byte 1 .byte 0 .byte 2 .byte 0 .byte 0 .byte 81 .byte 128 .byte 1 .byte 1 .byte 3 .byte 46 .byte 0 .byte 0 .byte 128 .byte 0 .byte 136 .byte 8 .byte 16 .byte 0 .byte 32 .byte 1 .byte 96 .byte 2 .byte 0 .byte 80 .byte 64 .byte 128 .byte 0 .byte 3 .byte 1 .byte 6 .byte 0 .byte 0 .byte 128 .byte 8 .byte 136 .byte 0 .byte 16 .byte 0 .byte 160 .byte 1 .byte 192 .byte 2 .byte 0 .byte 80 .byte 20 .byte 129 .byte 1 .byte 2 .byte 1 .byte 26 .byte 0 .byte 0 .byte 128 .text .global gift128b_init .type gift128b_init, @function gift128b_init: push r2 push r3 push r4 push r5 push r6 push r7 push r8 push r9 push r10 push r11 push r12 push r13 push r14 push r15 movw r30,r24 movw r26,r22 .L__stack_usage = 16 ld r15,X+ ld r14,X+ ld r13,X+ ld r12,X+ ld r7,X+ ld r6,X+ ld r5,X+ ld r4,X+ ld r11,X+ ld r10,X+ ld r9,X+ ld r8,X+ ld r3,X+ ld r2,X+ ld r23,X+ ld r22,X+ st Z,r22 std Z+1,r23 std Z+2,r2 std Z+3,r3 std Z+4,r4 std Z+5,r5 std Z+6,r6 std Z+7,r7 std Z+8,r8 std Z+9,r9 std Z+10,r10 std Z+11,r11 std Z+12,r12 std Z+13,r13 std Z+14,r14 std Z+15,r15 pop r15 pop r14 pop r13 pop r12 pop r11 pop r10 pop r9 pop r8 pop r7 pop r6 pop r5 pop r4 pop r3 pop r2 ret .size gift128b_init, .-gift128b_init .text .global gift128b_encrypt .type gift128b_encrypt, @function gift128b_encrypt: push r28 push r29 push r2 push r3 push r4 push r5 push r6 push r7 push r8 push r9 push r10 push r11 push r12 push r13 push r14 push r15 push r16 push r17 push r23 push r22 movw r30,r24 movw r26,r20 in r28,0x3d in r29,0x3e subi r28,80 sbci r29,0 in r0,0x3f cli out 0x3e,r29 out 0x3f,r0 out 0x3d,r28 .L__stack_usage = 100 ld r22,Z ldd r23,Z+1 ldd r2,Z+2 ldd r3,Z+3 ldd r4,Z+4 ldd r5,Z+5 ldd r6,Z+6 ldd r7,Z+7 ldd r8,Z+8 ldd r9,Z+9 ldd r10,Z+10 ldd r11,Z+11 ldd r12,Z+12 ldd r13,Z+13 ldd r14,Z+14 ldd r15,Z+15 movw r30,r28 adiw r30,1 st Z+,r22 st Z+,r23 st Z+,r2 st Z+,r3 st Z+,r4 st Z+,r5 st Z+,r6 st Z+,r7 st Z+,r8 st Z+,r9 st Z+,r10 st Z+,r11 st Z+,r12 st Z+,r13 st Z+,r14 st Z+,r15 ldi r24,4 35: st Z+,r4 st Z+,r5 st Z+,r6 st Z+,r7 lsl r22 rol r23 adc r22,r1 lsl r22 rol r23 adc r22,r1 lsl r22 rol r23 adc r22,r1 lsl r22 rol r23 adc r22,r1 mov r0,r1 lsr r3 ror r2 ror r0 lsr r3 ror r2 ror r0 or r3,r0 st Z+,r22 st Z+,r23 st Z+,r2 st Z+,r3 mov r0,r22 mov r22,r4 mov r4,r0 mov r0,r23 mov r23,r5 mov r5,r0 mov r0,r2 mov r2,r6 mov r6,r0 mov r0,r3 mov r3,r7 mov r7,r0 st Z+,r12 st Z+,r13 st Z+,r14 st Z+,r15 lsl r8 rol r9 adc r8,r1 lsl r8 rol r9 adc r8,r1 lsl r8 rol r9 adc r8,r1 lsl r8 rol r9 adc r8,r1 mov r0,r1 lsr r11 ror r10 ror r0 lsr r11 ror r10 ror r0 or r11,r0 st Z+,r8 st Z+,r9 st Z+,r10 st Z+,r11 mov r0,r8 mov r8,r12 mov r12,r0 mov r0,r9 mov r9,r13 mov r13,r0 mov r0,r10 mov r10,r14 mov r14,r0 mov r0,r11 mov r11,r15 mov r15,r0 dec r24 breq 5117f rjmp 35b 5117: subi r30,80 sbc r31,r1 ldi r24,2 121: ld r22,Z ldd r23,Z+1 ldd r2,Z+2 ldd r3,Z+3 movw r18,r22 movw r20,r2 mov r18,r19 mov r19,r20 mov r20,r21 mov r21,r1 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 eor r20,r2 eor r21,r3 andi r18,85 mov r19,r1 andi r20,85 mov r21,r1 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 mov r21,r20 mov r20,r19 mov r19,r18 mov r18,r1 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 movw r18,r22 movw r20,r2 mov r18,r19 mov r19,r20 mov r20,r21 mov r21,r1 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 eor r20,r2 eor r21,r3 andi r18,15 mov r19,r1 andi r20,15 mov r21,r1 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 mov r21,r20 mov r20,r19 mov r19,r18 mov r18,r1 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 movw r18,r22 movw r20,r2 movw r18,r20 mov r20,r1 mov r21,r1 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 andi r18,51 andi r19,51 eor r22,r18 eor r23,r19 mov r20,r1 mov r21,r1 movw r20,r18 mov r18,r1 mov r19,r1 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 st Z,r3 std Z+1,r23 std Z+2,r2 std Z+3,r22 ldd r22,Z+4 ldd r23,Z+5 ldd r2,Z+6 ldd r3,Z+7 movw r18,r22 movw r20,r2 mov r18,r19 mov r19,r20 mov r20,r21 mov r21,r1 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 eor r20,r2 eor r21,r3 andi r18,85 mov r19,r1 andi r20,85 mov r21,r1 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 mov r21,r20 mov r20,r19 mov r19,r18 mov r18,r1 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 movw r18,r22 movw r20,r2 mov r18,r19 mov r19,r20 mov r20,r21 mov r21,r1 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 eor r20,r2 eor r21,r3 andi r18,15 mov r19,r1 andi r20,15 mov r21,r1 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 mov r21,r20 mov r20,r19 mov r19,r18 mov r18,r1 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 movw r18,r22 movw r20,r2 movw r18,r20 mov r20,r1 mov r21,r1 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 andi r18,51 andi r19,51 eor r22,r18 eor r23,r19 mov r20,r1 mov r21,r1 movw r20,r18 mov r18,r1 mov r19,r1 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 std Z+4,r3 std Z+5,r23 std Z+6,r2 std Z+7,r22 ldd r22,Z+8 ldd r23,Z+9 ldd r2,Z+10 ldd r3,Z+11 movw r18,r22 movw r20,r2 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 eor r20,r2 eor r21,r3 andi r18,17 andi r19,17 andi r20,17 andi r21,17 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 movw r18,r22 movw r20,r2 mov r0,r1 lsl r18 rol r19 rol r20 rol r21 rol r0 lsl r18 rol r19 rol r20 rol r21 rol r0 mov r18,r19 mov r19,r20 mov r20,r21 mov r21,r0 eor r18,r22 eor r19,r23 eor r20,r2 eor r21,r3 andi r18,3 andi r19,3 andi r20,3 andi r21,3 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 mov r0,r1 lsr r21 ror r20 ror r19 ror r18 ror r0 lsr r21 ror r20 ror r19 ror r18 ror r0 mov r21,r20 mov r20,r19 mov r19,r18 mov r18,r0 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 movw r18,r22 movw r20,r2 mov r18,r19 mov r19,r20 mov r20,r21 mov r21,r1 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 eor r20,r2 eor r21,r3 andi r18,15 mov r19,r1 andi r20,15 mov r21,r1 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 mov r21,r20 mov r20,r19 mov r19,r18 mov r18,r1 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 std Z+8,r3 std Z+9,r23 std Z+10,r2 std Z+11,r22 ldd r22,Z+12 ldd r23,Z+13 ldd r2,Z+14 ldd r3,Z+15 movw r18,r22 movw r20,r2 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 eor r20,r2 eor r21,r3 andi r18,17 andi r19,17 andi r20,17 andi r21,17 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 movw r18,r22 movw r20,r2 mov r0,r1 lsl r18 rol r19 rol r20 rol r21 rol r0 lsl r18 rol r19 rol r20 rol r21 rol r0 mov r18,r19 mov r19,r20 mov r20,r21 mov r21,r0 eor r18,r22 eor r19,r23 eor r20,r2 eor r21,r3 andi r18,3 andi r19,3 andi r20,3 andi r21,3 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 mov r0,r1 lsr r21 ror r20 ror r19 ror r18 ror r0 lsr r21 ror r20 ror r19 ror r18 ror r0 mov r21,r20 mov r20,r19 mov r19,r18 mov r18,r0 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 movw r18,r22 movw r20,r2 mov r18,r19 mov r19,r20 mov r20,r21 mov r21,r1 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 eor r20,r2 eor r21,r3 andi r18,15 mov r19,r1 andi r20,15 mov r21,r1 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 mov r21,r20 mov r20,r19 mov r19,r18 mov r18,r1 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 std Z+12,r3 std Z+13,r23 std Z+14,r2 std Z+15,r22 ldd r22,Z+16 ldd r23,Z+17 ldd r2,Z+18 ldd r3,Z+19 movw r18,r22 movw r20,r2 mov r0,r1 lsl r19 rol r20 rol r21 rol r0 movw r18,r20 mov r20,r0 mov r21,r1 eor r18,r22 eor r19,r23 andi r18,170 andi r19,170 eor r22,r18 eor r23,r19 mov r20,r1 mov r21,r1 mov r0,r1 lsr r20 ror r19 ror r18 ror r0 movw r20,r18 mov r19,r0 mov r18,r1 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 movw r18,r22 movw r20,r2 movw r18,r20 mov r20,r1 mov r21,r1 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 andi r18,51 andi r19,51 eor r22,r18 eor r23,r19 mov r20,r1 mov r21,r1 movw r20,r18 mov r18,r1 mov r19,r1 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 movw r18,r22 movw r20,r2 mov r18,r19 mov r19,r20 mov r20,r21 mov r21,r1 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 andi r18,240 andi r19,240 eor r22,r18 eor r23,r19 mov r20,r1 mov r21,r1 mov r21,r20 mov r20,r19 mov r19,r18 mov r18,r1 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 std Z+16,r3 std Z+17,r23 std Z+18,r2 std Z+19,r22 ldd r22,Z+20 ldd r23,Z+21 ldd r2,Z+22 ldd r3,Z+23 movw r18,r22 movw r20,r2 mov r0,r1 lsl r19 rol r20 rol r21 rol r0 movw r18,r20 mov r20,r0 mov r21,r1 eor r18,r22 eor r19,r23 andi r18,170 andi r19,170 eor r22,r18 eor r23,r19 mov r20,r1 mov r21,r1 mov r0,r1 lsr r20 ror r19 ror r18 ror r0 movw r20,r18 mov r19,r0 mov r18,r1 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 movw r18,r22 movw r20,r2 movw r18,r20 mov r20,r1 mov r21,r1 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 andi r18,51 andi r19,51 eor r22,r18 eor r23,r19 mov r20,r1 mov r21,r1 movw r20,r18 mov r18,r1 mov r19,r1 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 movw r18,r22 movw r20,r2 mov r18,r19 mov r19,r20 mov r20,r21 mov r21,r1 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 andi r18,240 andi r19,240 eor r22,r18 eor r23,r19 mov r20,r1 mov r21,r1 mov r21,r20 mov r20,r19 mov r19,r18 mov r18,r1 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 std Z+20,r3 std Z+21,r23 std Z+22,r2 std Z+23,r22 ldd r22,Z+24 ldd r23,Z+25 ldd r2,Z+26 ldd r3,Z+27 movw r18,r22 movw r20,r2 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 eor r20,r2 eor r21,r3 andi r18,10 andi r19,10 andi r20,10 andi r21,10 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 movw r18,r22 movw r20,r2 mov r0,r1 lsl r18 rol r19 rol r20 rol r21 rol r0 lsl r18 rol r19 rol r20 rol r21 rol r0 mov r18,r19 mov r19,r20 mov r20,r21 mov r21,r0 eor r18,r22 eor r19,r23 eor r20,r2 eor r21,r3 andi r18,204 mov r19,r1 andi r20,204 mov r21,r1 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 mov r0,r1 lsr r21 ror r20 ror r19 ror r18 ror r0 lsr r21 ror r20 ror r19 ror r18 ror r0 mov r21,r20 mov r20,r19 mov r19,r18 mov r18,r0 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 movw r18,r22 movw r20,r2 mov r18,r19 mov r19,r20 mov r20,r21 mov r21,r1 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 andi r18,240 andi r19,240 eor r22,r18 eor r23,r19 mov r20,r1 mov r21,r1 mov r21,r20 mov r20,r19 mov r19,r18 mov r18,r1 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 std Z+24,r3 std Z+25,r23 std Z+26,r2 std Z+27,r22 ldd r22,Z+28 ldd r23,Z+29 ldd r2,Z+30 ldd r3,Z+31 movw r18,r22 movw r20,r2 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 eor r20,r2 eor r21,r3 andi r18,10 andi r19,10 andi r20,10 andi r21,10 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 movw r18,r22 movw r20,r2 mov r0,r1 lsl r18 rol r19 rol r20 rol r21 rol r0 lsl r18 rol r19 rol r20 rol r21 rol r0 mov r18,r19 mov r19,r20 mov r20,r21 mov r21,r0 eor r18,r22 eor r19,r23 eor r20,r2 eor r21,r3 andi r18,204 mov r19,r1 andi r20,204 mov r21,r1 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 mov r0,r1 lsr r21 ror r20 ror r19 ror r18 ror r0 lsr r21 ror r20 ror r19 ror r18 ror r0 mov r21,r20 mov r20,r19 mov r19,r18 mov r18,r0 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 movw r18,r22 movw r20,r2 mov r18,r19 mov r19,r20 mov r20,r21 mov r21,r1 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 andi r18,240 andi r19,240 eor r22,r18 eor r23,r19 mov r20,r1 mov r21,r1 mov r21,r20 mov r20,r19 mov r19,r18 mov r18,r1 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 std Z+28,r3 std Z+29,r23 std Z+30,r2 std Z+31,r22 dec r24 breq 1270f adiw r30,40 rjmp 121b 1270: ld r3,X+ ld r2,X+ ld r23,X+ ld r22,X+ ld r7,X+ ld r6,X+ ld r5,X+ ld r4,X+ ld r11,X+ ld r10,X+ ld r9,X+ ld r8,X+ ld r15,X+ ld r14,X+ ld r13,X+ ld r12,X+ movw r26,r28 adiw r26,1 ldi r30,lo8(table_0) ldi r31,hi8(table_0) #if defined(RAMPZ) ldi r24,hh8(table_0) in r0,_SFR_IO_ADDR(RAMPZ) push r0 out _SFR_IO_ADDR(RAMPZ),r24 #endif rcall 1329f #if defined(RAMPZ) pop r0 out _SFR_IO_ADDR(RAMPZ),r0 #endif rcall 2067f ldi r30,lo8(table_0) ldi r31,hi8(table_0) #if defined(RAMPZ) ldi r24,hh8(table_0) in r0,_SFR_IO_ADDR(RAMPZ) push r0 out _SFR_IO_ADDR(RAMPZ),r24 #endif ldi r30,20 adiw r26,40 rcall 1329f #if defined(RAMPZ) pop r0 out _SFR_IO_ADDR(RAMPZ),r0 #endif rcall 2067f ldi r30,lo8(table_0) ldi r31,hi8(table_0) #if defined(RAMPZ) ldi r24,hh8(table_0) in r0,_SFR_IO_ADDR(RAMPZ) push r0 out _SFR_IO_ADDR(RAMPZ),r24 #endif ldi r30,40 sbiw r26,40 rcall 1329f #if defined(RAMPZ) pop r0 out _SFR_IO_ADDR(RAMPZ),r0 #endif rcall 2067f ldi r30,lo8(table_0) ldi r31,hi8(table_0) #if defined(RAMPZ) ldi r24,hh8(table_0) in r0,_SFR_IO_ADDR(RAMPZ) push r0 out _SFR_IO_ADDR(RAMPZ),r24 #endif ldi r30,60 adiw r26,40 rcall 1329f #if defined(RAMPZ) pop r0 out _SFR_IO_ADDR(RAMPZ),r0 #endif rcall 2067f ldi r30,lo8(table_0) ldi r31,hi8(table_0) #if defined(RAMPZ) ldi r24,hh8(table_0) in r0,_SFR_IO_ADDR(RAMPZ) push r0 out _SFR_IO_ADDR(RAMPZ),r24 #endif ldi r30,80 sbiw r26,40 rcall 1329f #if defined(RAMPZ) pop r0 out _SFR_IO_ADDR(RAMPZ),r0 #endif rcall 2067f ldi r30,lo8(table_0) ldi r31,hi8(table_0) #if defined(RAMPZ) ldi r24,hh8(table_0) in r0,_SFR_IO_ADDR(RAMPZ) push r0 out _SFR_IO_ADDR(RAMPZ),r24 #endif ldi r30,100 adiw r26,40 rcall 1329f #if defined(RAMPZ) pop r0 out _SFR_IO_ADDR(RAMPZ),r0 #endif rcall 2067f ldi r30,lo8(table_0) ldi r31,hi8(table_0) #if defined(RAMPZ) ldi r24,hh8(table_0) in r0,_SFR_IO_ADDR(RAMPZ) push r0 out _SFR_IO_ADDR(RAMPZ),r24 #endif ldi r30,120 sbiw r26,40 rcall 1329f rcall 1329f rjmp 2541f 1329: mov r0,r22 and r0,r8 eor r4,r0 mov r0,r23 and r0,r9 eor r5,r0 mov r0,r2 and r0,r10 eor r6,r0 mov r0,r3 and r0,r11 eor r7,r0 mov r0,r4 and r0,r12 eor r22,r0 mov r0,r5 and r0,r13 eor r23,r0 mov r0,r6 and r0,r14 eor r2,r0 mov r0,r7 and r0,r15 eor r3,r0 mov r0,r22 or r0,r4 eor r8,r0 mov r0,r23 or r0,r5 eor r9,r0 mov r0,r2 or r0,r6 eor r10,r0 mov r0,r3 or r0,r7 eor r11,r0 eor r12,r8 eor r13,r9 eor r14,r10 eor r15,r11 eor r4,r12 eor r5,r13 eor r6,r14 eor r7,r15 com r12 com r13 com r14 com r15 mov r0,r22 and r0,r4 eor r8,r0 mov r0,r23 and r0,r5 eor r9,r0 mov r0,r2 and r0,r6 eor r10,r0 mov r0,r3 and r0,r7 eor r11,r0 movw r18,r4 movw r20,r6 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 andi r18,204 andi r19,204 andi r20,204 andi r21,204 lsr r7 ror r6 ror r5 ror r4 lsr r7 ror r6 ror r5 ror r4 ldi r25,51 and r4,r25 and r5,r25 and r6,r25 and r7,r25 or r4,r18 or r5,r19 or r6,r20 or r7,r21 movw r18,r8 movw r20,r10 lsl r18 rol r19 rol r20 rol r21 andi r18,238 andi r19,238 andi r20,238 andi r21,238 lsr r11 ror r10 ror r9 ror r8 lsr r11 ror r10 ror r9 ror r8 lsr r11 ror r10 ror r9 ror r8 ldi r24,17 and r8,r24 and r9,r24 and r10,r24 and r11,r24 or r8,r18 or r9,r19 or r10,r20 or r11,r21 movw r18,r12 movw r20,r14 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 andi r18,136 andi r19,136 andi r20,136 andi r21,136 lsr r15 ror r14 ror r13 ror r12 ldi r17,119 and r12,r17 and r13,r17 and r14,r17 and r15,r17 or r12,r18 or r13,r19 or r14,r20 or r15,r21 ld r18,X+ ld r19,X+ ld r20,X+ ld r21,X+ eor r4,r18 eor r5,r19 eor r6,r20 eor r7,r21 ld r18,X+ ld r19,X+ ld r20,X+ ld r21,X+ eor r8,r18 eor r9,r19 eor r10,r20 eor r11,r21 #if defined(RAMPZ) elpm r18,Z #elif defined(__AVR_HAVE_LPMX__) lpm r18,Z #elif defined(__AVR_TINY__) ld r18,Z #else lpm mov r18,r0 #endif inc r30 #if defined(RAMPZ) elpm r19,Z #elif defined(__AVR_HAVE_LPMX__) lpm r19,Z #elif defined(__AVR_TINY__) ld r19,Z #else lpm mov r19,r0 #endif inc r30 #if defined(RAMPZ) elpm r20,Z #elif defined(__AVR_HAVE_LPMX__) lpm r20,Z #elif defined(__AVR_TINY__) ld r20,Z #else lpm mov r20,r0 #endif inc r30 #if defined(RAMPZ) elpm r21,Z #elif defined(__AVR_HAVE_LPMX__) lpm r21,Z #elif defined(__AVR_TINY__) ld r21,Z #else lpm mov r21,r0 #endif inc r30 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 mov r0,r12 and r0,r8 eor r4,r0 mov r0,r13 and r0,r9 eor r5,r0 mov r0,r14 and r0,r10 eor r6,r0 mov r0,r15 and r0,r11 eor r7,r0 mov r0,r4 and r0,r22 eor r12,r0 mov r0,r5 and r0,r23 eor r13,r0 mov r0,r6 and r0,r2 eor r14,r0 mov r0,r7 and r0,r3 eor r15,r0 mov r0,r12 or r0,r4 eor r8,r0 mov r0,r13 or r0,r5 eor r9,r0 mov r0,r14 or r0,r6 eor r10,r0 mov r0,r15 or r0,r7 eor r11,r0 eor r22,r8 eor r23,r9 eor r2,r10 eor r3,r11 eor r4,r22 eor r5,r23 eor r6,r2 eor r7,r3 com r22 com r23 com r2 com r3 mov r0,r12 and r0,r4 eor r8,r0 mov r0,r13 and r0,r5 eor r9,r0 mov r0,r14 and r0,r6 eor r10,r0 mov r0,r15 and r0,r7 eor r11,r0 mov r0,r1 lsr r23 ror r22 ror r0 lsr r23 ror r22 ror r0 lsr r23 ror r22 ror r0 lsr r23 ror r22 ror r0 or r23,r0 mov r0,r1 lsr r3 ror r2 ror r0 lsr r3 ror r2 ror r0 lsr r3 ror r2 ror r0 lsr r3 ror r2 ror r0 or r3,r0 mov r0,r5 mov r5,r4 mov r4,r0 mov r0,r7 mov r7,r6 mov r6,r0 lsl r8 rol r9 adc r8,r1 lsl r8 rol r9 adc r8,r1 lsl r8 rol r9 adc r8,r1 lsl r8 rol r9 adc r8,r1 lsl r10 rol r11 adc r10,r1 lsl r10 rol r11 adc r10,r1 lsl r10 rol r11 adc r10,r1 lsl r10 rol r11 adc r10,r1 ld r18,X+ ld r19,X+ ld r20,X+ ld r21,X+ eor r4,r18 eor r5,r19 eor r6,r20 eor r7,r21 ld r18,X+ ld r19,X+ ld r20,X+ ld r21,X+ eor r8,r18 eor r9,r19 eor r10,r20 eor r11,r21 #if defined(RAMPZ) elpm r18,Z #elif defined(__AVR_HAVE_LPMX__) lpm r18,Z #elif defined(__AVR_TINY__) ld r18,Z #else lpm mov r18,r0 #endif inc r30 #if defined(RAMPZ) elpm r19,Z #elif defined(__AVR_HAVE_LPMX__) lpm r19,Z #elif defined(__AVR_TINY__) ld r19,Z #else lpm mov r19,r0 #endif inc r30 #if defined(RAMPZ) elpm r20,Z #elif defined(__AVR_HAVE_LPMX__) lpm r20,Z #elif defined(__AVR_TINY__) ld r20,Z #else lpm mov r20,r0 #endif inc r30 #if defined(RAMPZ) elpm r21,Z #elif defined(__AVR_HAVE_LPMX__) lpm r21,Z #elif defined(__AVR_TINY__) ld r21,Z #else lpm mov r21,r0 #endif inc r30 eor r12,r18 eor r13,r19 eor r14,r20 eor r15,r21 mov r0,r22 and r0,r8 eor r4,r0 mov r0,r23 and r0,r9 eor r5,r0 mov r0,r2 and r0,r10 eor r6,r0 mov r0,r3 and r0,r11 eor r7,r0 mov r0,r4 and r0,r12 eor r22,r0 mov r0,r5 and r0,r13 eor r23,r0 mov r0,r6 and r0,r14 eor r2,r0 mov r0,r7 and r0,r15 eor r3,r0 mov r0,r22 or r0,r4 eor r8,r0 mov r0,r23 or r0,r5 eor r9,r0 mov r0,r2 or r0,r6 eor r10,r0 mov r0,r3 or r0,r7 eor r11,r0 eor r12,r8 eor r13,r9 eor r14,r10 eor r15,r11 eor r4,r12 eor r5,r13 eor r6,r14 eor r7,r15 com r12 com r13 com r14 com r15 mov r0,r22 and r0,r4 eor r8,r0 mov r0,r23 and r0,r5 eor r9,r0 mov r0,r2 and r0,r6 eor r10,r0 mov r0,r3 and r0,r7 eor r11,r0 movw r18,r4 movw r20,r6 lsr r21 ror r20 ror r19 ror r18 eor r18,r4 eor r19,r5 eor r20,r6 eor r21,r7 andi r18,85 andi r19,85 andi r20,85 andi r21,85 eor r4,r18 eor r5,r19 eor r6,r20 eor r7,r21 lsl r18 rol r19 rol r20 rol r21 eor r4,r18 eor r5,r19 eor r6,r20 eor r7,r21 mov r0,r10 mov r10,r8 mov r8,r0 mov r0,r11 mov r11,r9 mov r9,r0 movw r18,r8 movw r20,r10 lsr r21 ror r20 ror r19 ror r18 eor r18,r8 eor r19,r9 andi r18,85 andi r19,85 eor r8,r18 eor r9,r19 mov r20,r1 mov r21,r1 lsl r18 rol r19 rol r20 rol r21 eor r8,r18 eor r9,r19 eor r10,r20 eor r11,r21 mov r0,r14 mov r14,r12 mov r12,r0 mov r0,r15 mov r15,r13 mov r13,r0 movw r18,r14 lsr r19 ror r18 eor r18,r14 eor r19,r15 andi r18,85 andi r19,85 eor r14,r18 eor r15,r19 lsl r18 rol r19 eor r14,r18 eor r15,r19 ld r18,X+ ld r19,X+ ld r20,X+ ld r21,X+ eor r4,r18 eor r5,r19 eor r6,r20 eor r7,r21 ld r18,X+ ld r19,X+ ld r20,X+ ld r21,X+ eor r8,r18 eor r9,r19 eor r10,r20 eor r11,r21 #if defined(RAMPZ) elpm r18,Z #elif defined(__AVR_HAVE_LPMX__) lpm r18,Z #elif defined(__AVR_TINY__) ld r18,Z #else lpm mov r18,r0 #endif inc r30 #if defined(RAMPZ) elpm r19,Z #elif defined(__AVR_HAVE_LPMX__) lpm r19,Z #elif defined(__AVR_TINY__) ld r19,Z #else lpm mov r19,r0 #endif inc r30 #if defined(RAMPZ) elpm r20,Z #elif defined(__AVR_HAVE_LPMX__) lpm r20,Z #elif defined(__AVR_TINY__) ld r20,Z #else lpm mov r20,r0 #endif inc r30 #if defined(RAMPZ) elpm r21,Z #elif defined(__AVR_HAVE_LPMX__) lpm r21,Z #elif defined(__AVR_TINY__) ld r21,Z #else lpm mov r21,r0 #endif inc r30 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 mov r0,r12 and r0,r8 eor r4,r0 mov r0,r13 and r0,r9 eor r5,r0 mov r0,r14 and r0,r10 eor r6,r0 mov r0,r15 and r0,r11 eor r7,r0 mov r0,r4 and r0,r22 eor r12,r0 mov r0,r5 and r0,r23 eor r13,r0 mov r0,r6 and r0,r2 eor r14,r0 mov r0,r7 and r0,r3 eor r15,r0 mov r0,r12 or r0,r4 eor r8,r0 mov r0,r13 or r0,r5 eor r9,r0 mov r0,r14 or r0,r6 eor r10,r0 mov r0,r15 or r0,r7 eor r11,r0 eor r22,r8 eor r23,r9 eor r2,r10 eor r3,r11 eor r4,r22 eor r5,r23 eor r6,r2 eor r7,r3 com r22 com r23 com r2 com r3 mov r0,r12 and r0,r4 eor r8,r0 mov r0,r13 and r0,r5 eor r9,r0 mov r0,r14 and r0,r6 eor r10,r0 mov r0,r15 and r0,r7 eor r11,r0 lsl r22 adc r22,r1 lsl r22 adc r22,r1 lsl r23 adc r23,r1 lsl r23 adc r23,r1 lsl r2 adc r2,r1 lsl r2 adc r2,r1 lsl r3 adc r3,r1 lsl r3 adc r3,r1 swap r4 swap r5 swap r6 swap r7 mov r0,r1 lsr r8 ror r0 lsr r8 ror r0 or r8,r0 mov r0,r1 lsr r9 ror r0 lsr r9 ror r0 or r9,r0 mov r0,r1 lsr r10 ror r0 lsr r10 ror r0 or r10,r0 mov r0,r1 lsr r11 ror r0 lsr r11 ror r0 or r11,r0 ld r18,X+ ld r19,X+ ld r20,X+ ld r21,X+ eor r4,r18 eor r5,r19 eor r6,r20 eor r7,r21 ld r18,X+ ld r19,X+ ld r20,X+ ld r21,X+ eor r8,r18 eor r9,r19 eor r10,r20 eor r11,r21 #if defined(RAMPZ) elpm r18,Z #elif defined(__AVR_HAVE_LPMX__) lpm r18,Z #elif defined(__AVR_TINY__) ld r18,Z #else lpm mov r18,r0 #endif inc r30 #if defined(RAMPZ) elpm r19,Z #elif defined(__AVR_HAVE_LPMX__) lpm r19,Z #elif defined(__AVR_TINY__) ld r19,Z #else lpm mov r19,r0 #endif inc r30 #if defined(RAMPZ) elpm r20,Z #elif defined(__AVR_HAVE_LPMX__) lpm r20,Z #elif defined(__AVR_TINY__) ld r20,Z #else lpm mov r20,r0 #endif inc r30 #if defined(RAMPZ) elpm r21,Z #elif defined(__AVR_HAVE_LPMX__) lpm r21,Z #elif defined(__AVR_TINY__) ld r21,Z #else lpm mov r21,r0 #endif inc r30 eor r12,r18 eor r13,r19 eor r14,r20 eor r15,r21 mov r0,r22 and r0,r8 eor r4,r0 mov r0,r23 and r0,r9 eor r5,r0 mov r0,r2 and r0,r10 eor r6,r0 mov r0,r3 and r0,r11 eor r7,r0 mov r0,r4 and r0,r12 eor r22,r0 mov r0,r5 and r0,r13 eor r23,r0 mov r0,r6 and r0,r14 eor r2,r0 mov r0,r7 and r0,r15 eor r3,r0 mov r0,r22 or r0,r4 eor r8,r0 mov r0,r23 or r0,r5 eor r9,r0 mov r0,r2 or r0,r6 eor r10,r0 mov r0,r3 or r0,r7 eor r11,r0 eor r12,r8 eor r13,r9 eor r14,r10 eor r15,r11 eor r4,r12 eor r5,r13 eor r6,r14 eor r7,r15 com r12 com r13 com r14 com r15 mov r0,r22 and r0,r4 eor r8,r0 mov r0,r23 and r0,r5 eor r9,r0 mov r0,r2 and r0,r6 eor r10,r0 mov r0,r3 and r0,r7 eor r11,r0 mov r0,r6 mov r6,r4 mov r4,r0 mov r0,r7 mov r7,r5 mov r5,r0 mov r0,r8 mov r8,r9 mov r9,r10 mov r10,r11 mov r11,r0 mov r0,r15 mov r15,r14 mov r14,r13 mov r13,r12 mov r12,r0 ld r18,X+ ld r19,X+ ld r20,X+ ld r21,X+ eor r4,r18 eor r5,r19 eor r6,r20 eor r7,r21 ld r18,X+ ld r19,X+ ld r20,X+ ld r21,X+ eor r8,r18 eor r9,r19 eor r10,r20 eor r11,r21 #if defined(RAMPZ) elpm r18,Z #elif defined(__AVR_HAVE_LPMX__) lpm r18,Z #elif defined(__AVR_TINY__) ld r18,Z #else lpm mov r18,r0 #endif inc r30 #if defined(RAMPZ) elpm r19,Z #elif defined(__AVR_HAVE_LPMX__) lpm r19,Z #elif defined(__AVR_TINY__) ld r19,Z #else lpm mov r19,r0 #endif inc r30 #if defined(RAMPZ) elpm r20,Z #elif defined(__AVR_HAVE_LPMX__) lpm r20,Z #elif defined(__AVR_TINY__) ld r20,Z #else lpm mov r20,r0 #endif inc r30 #if defined(RAMPZ) elpm r21,Z #elif defined(__AVR_HAVE_LPMX__) lpm r21,Z #elif defined(__AVR_TINY__) ld r21,Z #else lpm mov r21,r0 #endif inc r30 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 eor r22,r12 eor r23,r13 eor r2,r14 eor r3,r15 eor r12,r22 eor r13,r23 eor r14,r2 eor r15,r3 eor r22,r12 eor r23,r13 eor r2,r14 eor r3,r15 ret 2067: movw r30,r26 sbiw r30,40 push r3 push r2 push r23 push r22 push r7 push r6 push r5 push r4 ld r22,Z ldd r23,Z+1 ldd r2,Z+2 ldd r3,Z+3 ldd r26,Z+4 ldd r27,Z+5 ldd r24,Z+6 ldd r25,Z+7 movw r18,r26 movw r20,r24 movw r18,r20 mov r20,r1 mov r21,r1 eor r18,r26 eor r19,r27 andi r18,51 andi r19,51 eor r26,r18 eor r27,r19 mov r20,r1 mov r21,r1 movw r20,r18 mov r18,r1 mov r19,r1 eor r26,r18 eor r27,r19 eor r24,r20 eor r25,r21 movw r18,r26 movw r20,r24 lsr r21 ror r20 ror r19 ror r18 eor r18,r26 eor r19,r27 eor r20,r24 eor r21,r25 andi r18,68 andi r19,68 andi r20,85 andi r21,85 eor r26,r18 eor r27,r19 eor r24,r20 eor r25,r21 lsl r18 rol r19 rol r20 rol r21 eor r26,r18 eor r27,r19 eor r24,r20 eor r25,r21 st Z,r26 std Z+1,r27 std Z+2,r24 std Z+3,r25 movw r18,r22 movw r20,r2 andi r18,51 andi r19,51 andi r20,51 andi r21,51 andi r22,204 andi r23,204 ldi r17,204 and r2,r17 and r3,r17 or r2,r21 or r3,r18 or r22,r19 or r23,r20 movw r18,r2 movw r20,r22 lsr r21 ror r20 ror r19 ror r18 eor r18,r2 eor r19,r3 eor r20,r22 eor r21,r23 mov r18,r1 andi r19,17 andi r20,85 andi r21,85 eor r2,r18 eor r3,r19 eor r22,r20 eor r23,r21 lsl r18 rol r19 rol r20 rol r21 eor r2,r18 eor r3,r19 eor r22,r20 eor r23,r21 std Z+4,r2 std Z+5,r3 std Z+6,r22 std Z+7,r23 ldd r22,Z+8 ldd r23,Z+9 ldd r2,Z+10 ldd r3,Z+11 ldd r26,Z+12 ldd r27,Z+13 ldd r24,Z+14 ldd r25,Z+15 lsl r26 adc r26,r1 lsl r26 adc r26,r1 swap r27 lsl r24 adc r24,r1 lsl r24 adc r24,r1 swap r25 std Z+8,r26 std Z+9,r27 std Z+10,r24 std Z+11,r25 lsl r22 adc r22,r1 lsl r22 adc r22,r1 lsl r22 adc r22,r1 lsl r23 adc r23,r1 lsl r23 adc r23,r1 lsl r2 adc r2,r1 lsl r2 adc r2,r1 lsl r2 adc r2,r1 lsl r3 adc r3,r1 lsl r3 adc r3,r1 std Z+12,r22 std Z+13,r23 std Z+14,r2 std Z+15,r3 ldd r22,Z+16 ldd r23,Z+17 ldd r2,Z+18 ldd r3,Z+19 ldd r26,Z+20 ldd r27,Z+21 ldd r24,Z+22 ldd r25,Z+23 movw r18,r26 movw r20,r24 andi r18,170 andi r19,170 andi r20,170 andi r21,170 andi r26,85 andi r27,85 andi r24,85 andi r25,85 or r26,r19 or r27,r20 or r24,r21 or r25,r18 std Z+16,r24 std Z+17,r25 std Z+18,r26 std Z+19,r27 movw r18,r22 movw r20,r2 andi r18,85 andi r19,85 andi r20,85 andi r21,85 andi r22,170 andi r23,170 ldi r16,170 and r2,r16 and r3,r16 lsl r22 rol r23 rol r2 rol r3 adc r22,r1 lsl r22 rol r23 rol r2 rol r3 adc r22,r1 lsl r22 rol r23 rol r2 rol r3 adc r22,r1 lsl r22 rol r23 rol r2 rol r3 adc r22,r1 or r22,r18 or r23,r19 or r2,r20 or r3,r21 std Z+20,r3 std Z+21,r22 std Z+22,r23 std Z+23,r2 ldd r22,Z+24 ldd r23,Z+25 ldd r2,Z+26 ldd r3,Z+27 ldd r26,Z+28 ldd r27,Z+29 ldd r24,Z+30 ldd r25,Z+31 movw r18,r26 movw r20,r24 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 eor r18,r26 eor r19,r27 eor r20,r24 eor r21,r25 andi r18,3 andi r19,3 andi r20,3 andi r21,3 eor r26,r18 eor r27,r19 eor r24,r20 eor r25,r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 eor r26,r18 eor r27,r19 eor r24,r20 eor r25,r21 movw r18,r26 movw r20,r24 lsr r21 ror r20 ror r19 ror r18 andi r18,120 andi r19,120 andi r20,120 andi r21,120 movw r4,r18 movw r6,r20 lsr r7 ror r6 ror r5 ror r4 lsr r7 ror r6 ror r5 ror r4 lsr r7 ror r6 ror r5 ror r4 lsr r7 ror r6 ror r5 ror r4 eor r4,r18 eor r5,r19 eor r6,r20 eor r7,r21 ldi r16,8 and r4,r16 and r5,r16 and r6,r16 and r7,r16 eor r18,r4 eor r19,r5 eor r20,r6 eor r21,r7 lsl r4 rol r5 rol r6 rol r7 lsl r4 rol r5 rol r6 rol r7 lsl r4 rol r5 rol r6 rol r7 lsl r4 rol r5 rol r6 rol r7 eor r18,r4 eor r19,r5 eor r20,r6 eor r21,r7 andi r26,15 andi r27,15 andi r24,15 andi r25,15 or r26,r18 or r27,r19 or r24,r20 or r25,r21 std Z+24,r26 std Z+25,r27 std Z+26,r24 std Z+27,r25 movw r18,r2 lsr r19 ror r18 lsr r19 ror r18 andi r18,48 andi r19,48 movw r26,r22 movw r24,r2 andi r26,1 andi r27,1 andi r24,1 andi r25,1 lsl r26 rol r27 rol r24 rol r25 lsl r26 rol r27 rol r24 rol r25 lsl r26 rol r27 rol r24 rol r25 or r26,r18 or r27,r19 movw r18,r2 lsl r18 rol r19 lsl r18 rol r19 andi r18,192 andi r19,192 or r26,r18 or r27,r19 movw r18,r22 andi r18,224 andi r19,224 lsr r19 ror r18 or r24,r18 or r25,r19 movw r18,r22 movw r20,r2 lsr r21 ror r20 ror r19 ror r18 andi r18,7 andi r19,7 andi r20,7 andi r21,7 or r26,r18 or r27,r19 or r24,r20 or r25,r21 andi r22,16 andi r23,16 lsl r22 rol r23 lsl r22 rol r23 lsl r22 rol r23 or r24,r22 or r25,r23 std Z+28,r26 std Z+29,r27 std Z+30,r24 std Z+31,r25 ldd r22,Z+32 ldd r23,Z+33 ldd r2,Z+34 ldd r3,Z+35 ldd r26,Z+36 ldd r27,Z+37 ldd r24,Z+38 ldd r25,Z+39 mov r0,r1 lsr r25 ror r24 ror r0 lsr r25 ror r24 ror r0 lsr r25 ror r24 ror r0 lsr r25 ror r24 ror r0 or r25,r0 std Z+32,r27 std Z+33,r26 std Z+34,r24 std Z+35,r25 mov r0,r1 lsr r23 ror r22 ror r0 lsr r23 ror r22 ror r0 lsr r23 ror r22 ror r0 lsr r23 ror r22 ror r0 or r23,r0 mov r0,r2 mov r2,r3 mov r3,r0 lsl r2 rol r3 adc r2,r1 lsl r2 rol r3 adc r2,r1 std Z+36,r22 std Z+37,r23 std Z+38,r2 std Z+39,r3 pop r4 pop r5 pop r6 pop r7 pop r22 pop r23 pop r2 pop r3 movw r26,r30 ret 2541: #if defined(RAMPZ) pop r0 out _SFR_IO_ADDR(RAMPZ),r0 #endif subi r28,175 sbci r29,255 ld r26,Y+ ld r27,Y subi r28,82 sbc r29,r1 st X+,r3 st X+,r2 st X+,r23 st X+,r22 st X+,r7 st X+,r6 st X+,r5 st X+,r4 st X+,r11 st X+,r10 st X+,r9 st X+,r8 st X+,r15 st X+,r14 st X+,r13 st X+,r12 subi r28,174 sbci r29,255 in r0,0x3f cli out 0x3e,r29 out 0x3f,r0 out 0x3d,r28 pop r17 pop r16 pop r15 pop r14 pop r13 pop r12 pop r11 pop r10 pop r9 pop r8 pop r7 pop r6 pop r5 pop r4 pop r3 pop r2 pop r29 pop r28 ret .size gift128b_encrypt, .-gift128b_encrypt .text .global gift128b_encrypt_preloaded .type gift128b_encrypt_preloaded, @function gift128b_encrypt_preloaded: push r28 push r29 push r2 push r3 push r4 push r5 push r6 push r7 push r8 push r9 push r10 push r11 push r12 push r13 push r14 push r15 push r16 push r17 push r23 push r22 movw r30,r24 movw r26,r20 in r28,0x3d in r29,0x3e subi r28,80 sbci r29,0 in r0,0x3f cli out 0x3e,r29 out 0x3f,r0 out 0x3d,r28 .L__stack_usage = 100 ld r22,Z ldd r23,Z+1 ldd r2,Z+2 ldd r3,Z+3 ldd r4,Z+4 ldd r5,Z+5 ldd r6,Z+6 ldd r7,Z+7 ldd r8,Z+8 ldd r9,Z+9 ldd r10,Z+10 ldd r11,Z+11 ldd r12,Z+12 ldd r13,Z+13 ldd r14,Z+14 ldd r15,Z+15 movw r30,r28 adiw r30,1 st Z+,r22 st Z+,r23 st Z+,r2 st Z+,r3 st Z+,r4 st Z+,r5 st Z+,r6 st Z+,r7 st Z+,r8 st Z+,r9 st Z+,r10 st Z+,r11 st Z+,r12 st Z+,r13 st Z+,r14 st Z+,r15 ldi r24,4 35: st Z+,r4 st Z+,r5 st Z+,r6 st Z+,r7 lsl r22 rol r23 adc r22,r1 lsl r22 rol r23 adc r22,r1 lsl r22 rol r23 adc r22,r1 lsl r22 rol r23 adc r22,r1 mov r0,r1 lsr r3 ror r2 ror r0 lsr r3 ror r2 ror r0 or r3,r0 st Z+,r22 st Z+,r23 st Z+,r2 st Z+,r3 mov r0,r22 mov r22,r4 mov r4,r0 mov r0,r23 mov r23,r5 mov r5,r0 mov r0,r2 mov r2,r6 mov r6,r0 mov r0,r3 mov r3,r7 mov r7,r0 st Z+,r12 st Z+,r13 st Z+,r14 st Z+,r15 lsl r8 rol r9 adc r8,r1 lsl r8 rol r9 adc r8,r1 lsl r8 rol r9 adc r8,r1 lsl r8 rol r9 adc r8,r1 mov r0,r1 lsr r11 ror r10 ror r0 lsr r11 ror r10 ror r0 or r11,r0 st Z+,r8 st Z+,r9 st Z+,r10 st Z+,r11 mov r0,r8 mov r8,r12 mov r12,r0 mov r0,r9 mov r9,r13 mov r13,r0 mov r0,r10 mov r10,r14 mov r14,r0 mov r0,r11 mov r11,r15 mov r15,r0 dec r24 breq 5117f rjmp 35b 5117: subi r30,80 sbc r31,r1 ldi r24,2 121: ld r22,Z ldd r23,Z+1 ldd r2,Z+2 ldd r3,Z+3 movw r18,r22 movw r20,r2 mov r18,r19 mov r19,r20 mov r20,r21 mov r21,r1 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 eor r20,r2 eor r21,r3 andi r18,85 mov r19,r1 andi r20,85 mov r21,r1 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 mov r21,r20 mov r20,r19 mov r19,r18 mov r18,r1 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 movw r18,r22 movw r20,r2 mov r18,r19 mov r19,r20 mov r20,r21 mov r21,r1 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 eor r20,r2 eor r21,r3 andi r18,15 mov r19,r1 andi r20,15 mov r21,r1 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 mov r21,r20 mov r20,r19 mov r19,r18 mov r18,r1 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 movw r18,r22 movw r20,r2 movw r18,r20 mov r20,r1 mov r21,r1 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 andi r18,51 andi r19,51 eor r22,r18 eor r23,r19 mov r20,r1 mov r21,r1 movw r20,r18 mov r18,r1 mov r19,r1 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 st Z,r3 std Z+1,r23 std Z+2,r2 std Z+3,r22 ldd r22,Z+4 ldd r23,Z+5 ldd r2,Z+6 ldd r3,Z+7 movw r18,r22 movw r20,r2 mov r18,r19 mov r19,r20 mov r20,r21 mov r21,r1 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 eor r20,r2 eor r21,r3 andi r18,85 mov r19,r1 andi r20,85 mov r21,r1 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 mov r21,r20 mov r20,r19 mov r19,r18 mov r18,r1 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 movw r18,r22 movw r20,r2 mov r18,r19 mov r19,r20 mov r20,r21 mov r21,r1 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 eor r20,r2 eor r21,r3 andi r18,15 mov r19,r1 andi r20,15 mov r21,r1 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 mov r21,r20 mov r20,r19 mov r19,r18 mov r18,r1 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 movw r18,r22 movw r20,r2 movw r18,r20 mov r20,r1 mov r21,r1 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 andi r18,51 andi r19,51 eor r22,r18 eor r23,r19 mov r20,r1 mov r21,r1 movw r20,r18 mov r18,r1 mov r19,r1 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 std Z+4,r3 std Z+5,r23 std Z+6,r2 std Z+7,r22 ldd r22,Z+8 ldd r23,Z+9 ldd r2,Z+10 ldd r3,Z+11 movw r18,r22 movw r20,r2 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 eor r20,r2 eor r21,r3 andi r18,17 andi r19,17 andi r20,17 andi r21,17 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 movw r18,r22 movw r20,r2 mov r0,r1 lsl r18 rol r19 rol r20 rol r21 rol r0 lsl r18 rol r19 rol r20 rol r21 rol r0 mov r18,r19 mov r19,r20 mov r20,r21 mov r21,r0 eor r18,r22 eor r19,r23 eor r20,r2 eor r21,r3 andi r18,3 andi r19,3 andi r20,3 andi r21,3 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 mov r0,r1 lsr r21 ror r20 ror r19 ror r18 ror r0 lsr r21 ror r20 ror r19 ror r18 ror r0 mov r21,r20 mov r20,r19 mov r19,r18 mov r18,r0 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 movw r18,r22 movw r20,r2 mov r18,r19 mov r19,r20 mov r20,r21 mov r21,r1 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 eor r20,r2 eor r21,r3 andi r18,15 mov r19,r1 andi r20,15 mov r21,r1 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 mov r21,r20 mov r20,r19 mov r19,r18 mov r18,r1 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 std Z+8,r3 std Z+9,r23 std Z+10,r2 std Z+11,r22 ldd r22,Z+12 ldd r23,Z+13 ldd r2,Z+14 ldd r3,Z+15 movw r18,r22 movw r20,r2 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 eor r20,r2 eor r21,r3 andi r18,17 andi r19,17 andi r20,17 andi r21,17 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 movw r18,r22 movw r20,r2 mov r0,r1 lsl r18 rol r19 rol r20 rol r21 rol r0 lsl r18 rol r19 rol r20 rol r21 rol r0 mov r18,r19 mov r19,r20 mov r20,r21 mov r21,r0 eor r18,r22 eor r19,r23 eor r20,r2 eor r21,r3 andi r18,3 andi r19,3 andi r20,3 andi r21,3 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 mov r0,r1 lsr r21 ror r20 ror r19 ror r18 ror r0 lsr r21 ror r20 ror r19 ror r18 ror r0 mov r21,r20 mov r20,r19 mov r19,r18 mov r18,r0 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 movw r18,r22 movw r20,r2 mov r18,r19 mov r19,r20 mov r20,r21 mov r21,r1 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 eor r20,r2 eor r21,r3 andi r18,15 mov r19,r1 andi r20,15 mov r21,r1 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 mov r21,r20 mov r20,r19 mov r19,r18 mov r18,r1 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 std Z+12,r3 std Z+13,r23 std Z+14,r2 std Z+15,r22 ldd r22,Z+16 ldd r23,Z+17 ldd r2,Z+18 ldd r3,Z+19 movw r18,r22 movw r20,r2 mov r0,r1 lsl r19 rol r20 rol r21 rol r0 movw r18,r20 mov r20,r0 mov r21,r1 eor r18,r22 eor r19,r23 andi r18,170 andi r19,170 eor r22,r18 eor r23,r19 mov r20,r1 mov r21,r1 mov r0,r1 lsr r20 ror r19 ror r18 ror r0 movw r20,r18 mov r19,r0 mov r18,r1 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 movw r18,r22 movw r20,r2 movw r18,r20 mov r20,r1 mov r21,r1 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 andi r18,51 andi r19,51 eor r22,r18 eor r23,r19 mov r20,r1 mov r21,r1 movw r20,r18 mov r18,r1 mov r19,r1 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 movw r18,r22 movw r20,r2 mov r18,r19 mov r19,r20 mov r20,r21 mov r21,r1 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 andi r18,240 andi r19,240 eor r22,r18 eor r23,r19 mov r20,r1 mov r21,r1 mov r21,r20 mov r20,r19 mov r19,r18 mov r18,r1 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 std Z+16,r3 std Z+17,r23 std Z+18,r2 std Z+19,r22 ldd r22,Z+20 ldd r23,Z+21 ldd r2,Z+22 ldd r3,Z+23 movw r18,r22 movw r20,r2 mov r0,r1 lsl r19 rol r20 rol r21 rol r0 movw r18,r20 mov r20,r0 mov r21,r1 eor r18,r22 eor r19,r23 andi r18,170 andi r19,170 eor r22,r18 eor r23,r19 mov r20,r1 mov r21,r1 mov r0,r1 lsr r20 ror r19 ror r18 ror r0 movw r20,r18 mov r19,r0 mov r18,r1 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 movw r18,r22 movw r20,r2 movw r18,r20 mov r20,r1 mov r21,r1 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 andi r18,51 andi r19,51 eor r22,r18 eor r23,r19 mov r20,r1 mov r21,r1 movw r20,r18 mov r18,r1 mov r19,r1 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 movw r18,r22 movw r20,r2 mov r18,r19 mov r19,r20 mov r20,r21 mov r21,r1 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 andi r18,240 andi r19,240 eor r22,r18 eor r23,r19 mov r20,r1 mov r21,r1 mov r21,r20 mov r20,r19 mov r19,r18 mov r18,r1 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 std Z+20,r3 std Z+21,r23 std Z+22,r2 std Z+23,r22 ldd r22,Z+24 ldd r23,Z+25 ldd r2,Z+26 ldd r3,Z+27 movw r18,r22 movw r20,r2 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 eor r20,r2 eor r21,r3 andi r18,10 andi r19,10 andi r20,10 andi r21,10 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 movw r18,r22 movw r20,r2 mov r0,r1 lsl r18 rol r19 rol r20 rol r21 rol r0 lsl r18 rol r19 rol r20 rol r21 rol r0 mov r18,r19 mov r19,r20 mov r20,r21 mov r21,r0 eor r18,r22 eor r19,r23 eor r20,r2 eor r21,r3 andi r18,204 mov r19,r1 andi r20,204 mov r21,r1 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 mov r0,r1 lsr r21 ror r20 ror r19 ror r18 ror r0 lsr r21 ror r20 ror r19 ror r18 ror r0 mov r21,r20 mov r20,r19 mov r19,r18 mov r18,r0 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 movw r18,r22 movw r20,r2 mov r18,r19 mov r19,r20 mov r20,r21 mov r21,r1 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 andi r18,240 andi r19,240 eor r22,r18 eor r23,r19 mov r20,r1 mov r21,r1 mov r21,r20 mov r20,r19 mov r19,r18 mov r18,r1 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 std Z+24,r3 std Z+25,r23 std Z+26,r2 std Z+27,r22 ldd r22,Z+28 ldd r23,Z+29 ldd r2,Z+30 ldd r3,Z+31 movw r18,r22 movw r20,r2 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 eor r20,r2 eor r21,r3 andi r18,10 andi r19,10 andi r20,10 andi r21,10 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 movw r18,r22 movw r20,r2 mov r0,r1 lsl r18 rol r19 rol r20 rol r21 rol r0 lsl r18 rol r19 rol r20 rol r21 rol r0 mov r18,r19 mov r19,r20 mov r20,r21 mov r21,r0 eor r18,r22 eor r19,r23 eor r20,r2 eor r21,r3 andi r18,204 mov r19,r1 andi r20,204 mov r21,r1 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 mov r0,r1 lsr r21 ror r20 ror r19 ror r18 ror r0 lsr r21 ror r20 ror r19 ror r18 ror r0 mov r21,r20 mov r20,r19 mov r19,r18 mov r18,r0 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 movw r18,r22 movw r20,r2 mov r18,r19 mov r19,r20 mov r20,r21 mov r21,r1 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 andi r18,240 andi r19,240 eor r22,r18 eor r23,r19 mov r20,r1 mov r21,r1 mov r21,r20 mov r20,r19 mov r19,r18 mov r18,r1 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 std Z+28,r3 std Z+29,r23 std Z+30,r2 std Z+31,r22 dec r24 breq 1270f adiw r30,40 rjmp 121b 1270: ld r22,X+ ld r23,X+ ld r2,X+ ld r3,X+ ld r4,X+ ld r5,X+ ld r6,X+ ld r7,X+ ld r8,X+ ld r9,X+ ld r10,X+ ld r11,X+ ld r12,X+ ld r13,X+ ld r14,X+ ld r15,X+ movw r26,r28 adiw r26,1 ldi r30,lo8(table_0) ldi r31,hi8(table_0) #if defined(RAMPZ) ldi r24,hh8(table_0) in r0,_SFR_IO_ADDR(RAMPZ) push r0 out _SFR_IO_ADDR(RAMPZ),r24 #endif rcall 1329f #if defined(RAMPZ) pop r0 out _SFR_IO_ADDR(RAMPZ),r0 #endif rcall 2067f ldi r30,lo8(table_0) ldi r31,hi8(table_0) #if defined(RAMPZ) ldi r24,hh8(table_0) in r0,_SFR_IO_ADDR(RAMPZ) push r0 out _SFR_IO_ADDR(RAMPZ),r24 #endif ldi r30,20 adiw r26,40 rcall 1329f #if defined(RAMPZ) pop r0 out _SFR_IO_ADDR(RAMPZ),r0 #endif rcall 2067f ldi r30,lo8(table_0) ldi r31,hi8(table_0) #if defined(RAMPZ) ldi r24,hh8(table_0) in r0,_SFR_IO_ADDR(RAMPZ) push r0 out _SFR_IO_ADDR(RAMPZ),r24 #endif ldi r30,40 sbiw r26,40 rcall 1329f #if defined(RAMPZ) pop r0 out _SFR_IO_ADDR(RAMPZ),r0 #endif rcall 2067f ldi r30,lo8(table_0) ldi r31,hi8(table_0) #if defined(RAMPZ) ldi r24,hh8(table_0) in r0,_SFR_IO_ADDR(RAMPZ) push r0 out _SFR_IO_ADDR(RAMPZ),r24 #endif ldi r30,60 adiw r26,40 rcall 1329f #if defined(RAMPZ) pop r0 out _SFR_IO_ADDR(RAMPZ),r0 #endif rcall 2067f ldi r30,lo8(table_0) ldi r31,hi8(table_0) #if defined(RAMPZ) ldi r24,hh8(table_0) in r0,_SFR_IO_ADDR(RAMPZ) push r0 out _SFR_IO_ADDR(RAMPZ),r24 #endif ldi r30,80 sbiw r26,40 rcall 1329f #if defined(RAMPZ) pop r0 out _SFR_IO_ADDR(RAMPZ),r0 #endif rcall 2067f ldi r30,lo8(table_0) ldi r31,hi8(table_0) #if defined(RAMPZ) ldi r24,hh8(table_0) in r0,_SFR_IO_ADDR(RAMPZ) push r0 out _SFR_IO_ADDR(RAMPZ),r24 #endif ldi r30,100 adiw r26,40 rcall 1329f #if defined(RAMPZ) pop r0 out _SFR_IO_ADDR(RAMPZ),r0 #endif rcall 2067f ldi r30,lo8(table_0) ldi r31,hi8(table_0) #if defined(RAMPZ) ldi r24,hh8(table_0) in r0,_SFR_IO_ADDR(RAMPZ) push r0 out _SFR_IO_ADDR(RAMPZ),r24 #endif ldi r30,120 sbiw r26,40 rcall 1329f rcall 1329f rjmp 2541f 1329: mov r0,r22 and r0,r8 eor r4,r0 mov r0,r23 and r0,r9 eor r5,r0 mov r0,r2 and r0,r10 eor r6,r0 mov r0,r3 and r0,r11 eor r7,r0 mov r0,r4 and r0,r12 eor r22,r0 mov r0,r5 and r0,r13 eor r23,r0 mov r0,r6 and r0,r14 eor r2,r0 mov r0,r7 and r0,r15 eor r3,r0 mov r0,r22 or r0,r4 eor r8,r0 mov r0,r23 or r0,r5 eor r9,r0 mov r0,r2 or r0,r6 eor r10,r0 mov r0,r3 or r0,r7 eor r11,r0 eor r12,r8 eor r13,r9 eor r14,r10 eor r15,r11 eor r4,r12 eor r5,r13 eor r6,r14 eor r7,r15 com r12 com r13 com r14 com r15 mov r0,r22 and r0,r4 eor r8,r0 mov r0,r23 and r0,r5 eor r9,r0 mov r0,r2 and r0,r6 eor r10,r0 mov r0,r3 and r0,r7 eor r11,r0 movw r18,r4 movw r20,r6 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 andi r18,204 andi r19,204 andi r20,204 andi r21,204 lsr r7 ror r6 ror r5 ror r4 lsr r7 ror r6 ror r5 ror r4 ldi r25,51 and r4,r25 and r5,r25 and r6,r25 and r7,r25 or r4,r18 or r5,r19 or r6,r20 or r7,r21 movw r18,r8 movw r20,r10 lsl r18 rol r19 rol r20 rol r21 andi r18,238 andi r19,238 andi r20,238 andi r21,238 lsr r11 ror r10 ror r9 ror r8 lsr r11 ror r10 ror r9 ror r8 lsr r11 ror r10 ror r9 ror r8 ldi r24,17 and r8,r24 and r9,r24 and r10,r24 and r11,r24 or r8,r18 or r9,r19 or r10,r20 or r11,r21 movw r18,r12 movw r20,r14 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 andi r18,136 andi r19,136 andi r20,136 andi r21,136 lsr r15 ror r14 ror r13 ror r12 ldi r17,119 and r12,r17 and r13,r17 and r14,r17 and r15,r17 or r12,r18 or r13,r19 or r14,r20 or r15,r21 ld r18,X+ ld r19,X+ ld r20,X+ ld r21,X+ eor r4,r18 eor r5,r19 eor r6,r20 eor r7,r21 ld r18,X+ ld r19,X+ ld r20,X+ ld r21,X+ eor r8,r18 eor r9,r19 eor r10,r20 eor r11,r21 #if defined(RAMPZ) elpm r18,Z #elif defined(__AVR_HAVE_LPMX__) lpm r18,Z #elif defined(__AVR_TINY__) ld r18,Z #else lpm mov r18,r0 #endif inc r30 #if defined(RAMPZ) elpm r19,Z #elif defined(__AVR_HAVE_LPMX__) lpm r19,Z #elif defined(__AVR_TINY__) ld r19,Z #else lpm mov r19,r0 #endif inc r30 #if defined(RAMPZ) elpm r20,Z #elif defined(__AVR_HAVE_LPMX__) lpm r20,Z #elif defined(__AVR_TINY__) ld r20,Z #else lpm mov r20,r0 #endif inc r30 #if defined(RAMPZ) elpm r21,Z #elif defined(__AVR_HAVE_LPMX__) lpm r21,Z #elif defined(__AVR_TINY__) ld r21,Z #else lpm mov r21,r0 #endif inc r30 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 mov r0,r12 and r0,r8 eor r4,r0 mov r0,r13 and r0,r9 eor r5,r0 mov r0,r14 and r0,r10 eor r6,r0 mov r0,r15 and r0,r11 eor r7,r0 mov r0,r4 and r0,r22 eor r12,r0 mov r0,r5 and r0,r23 eor r13,r0 mov r0,r6 and r0,r2 eor r14,r0 mov r0,r7 and r0,r3 eor r15,r0 mov r0,r12 or r0,r4 eor r8,r0 mov r0,r13 or r0,r5 eor r9,r0 mov r0,r14 or r0,r6 eor r10,r0 mov r0,r15 or r0,r7 eor r11,r0 eor r22,r8 eor r23,r9 eor r2,r10 eor r3,r11 eor r4,r22 eor r5,r23 eor r6,r2 eor r7,r3 com r22 com r23 com r2 com r3 mov r0,r12 and r0,r4 eor r8,r0 mov r0,r13 and r0,r5 eor r9,r0 mov r0,r14 and r0,r6 eor r10,r0 mov r0,r15 and r0,r7 eor r11,r0 mov r0,r1 lsr r23 ror r22 ror r0 lsr r23 ror r22 ror r0 lsr r23 ror r22 ror r0 lsr r23 ror r22 ror r0 or r23,r0 mov r0,r1 lsr r3 ror r2 ror r0 lsr r3 ror r2 ror r0 lsr r3 ror r2 ror r0 lsr r3 ror r2 ror r0 or r3,r0 mov r0,r5 mov r5,r4 mov r4,r0 mov r0,r7 mov r7,r6 mov r6,r0 lsl r8 rol r9 adc r8,r1 lsl r8 rol r9 adc r8,r1 lsl r8 rol r9 adc r8,r1 lsl r8 rol r9 adc r8,r1 lsl r10 rol r11 adc r10,r1 lsl r10 rol r11 adc r10,r1 lsl r10 rol r11 adc r10,r1 lsl r10 rol r11 adc r10,r1 ld r18,X+ ld r19,X+ ld r20,X+ ld r21,X+ eor r4,r18 eor r5,r19 eor r6,r20 eor r7,r21 ld r18,X+ ld r19,X+ ld r20,X+ ld r21,X+ eor r8,r18 eor r9,r19 eor r10,r20 eor r11,r21 #if defined(RAMPZ) elpm r18,Z #elif defined(__AVR_HAVE_LPMX__) lpm r18,Z #elif defined(__AVR_TINY__) ld r18,Z #else lpm mov r18,r0 #endif inc r30 #if defined(RAMPZ) elpm r19,Z #elif defined(__AVR_HAVE_LPMX__) lpm r19,Z #elif defined(__AVR_TINY__) ld r19,Z #else lpm mov r19,r0 #endif inc r30 #if defined(RAMPZ) elpm r20,Z #elif defined(__AVR_HAVE_LPMX__) lpm r20,Z #elif defined(__AVR_TINY__) ld r20,Z #else lpm mov r20,r0 #endif inc r30 #if defined(RAMPZ) elpm r21,Z #elif defined(__AVR_HAVE_LPMX__) lpm r21,Z #elif defined(__AVR_TINY__) ld r21,Z #else lpm mov r21,r0 #endif inc r30 eor r12,r18 eor r13,r19 eor r14,r20 eor r15,r21 mov r0,r22 and r0,r8 eor r4,r0 mov r0,r23 and r0,r9 eor r5,r0 mov r0,r2 and r0,r10 eor r6,r0 mov r0,r3 and r0,r11 eor r7,r0 mov r0,r4 and r0,r12 eor r22,r0 mov r0,r5 and r0,r13 eor r23,r0 mov r0,r6 and r0,r14 eor r2,r0 mov r0,r7 and r0,r15 eor r3,r0 mov r0,r22 or r0,r4 eor r8,r0 mov r0,r23 or r0,r5 eor r9,r0 mov r0,r2 or r0,r6 eor r10,r0 mov r0,r3 or r0,r7 eor r11,r0 eor r12,r8 eor r13,r9 eor r14,r10 eor r15,r11 eor r4,r12 eor r5,r13 eor r6,r14 eor r7,r15 com r12 com r13 com r14 com r15 mov r0,r22 and r0,r4 eor r8,r0 mov r0,r23 and r0,r5 eor r9,r0 mov r0,r2 and r0,r6 eor r10,r0 mov r0,r3 and r0,r7 eor r11,r0 movw r18,r4 movw r20,r6 lsr r21 ror r20 ror r19 ror r18 eor r18,r4 eor r19,r5 eor r20,r6 eor r21,r7 andi r18,85 andi r19,85 andi r20,85 andi r21,85 eor r4,r18 eor r5,r19 eor r6,r20 eor r7,r21 lsl r18 rol r19 rol r20 rol r21 eor r4,r18 eor r5,r19 eor r6,r20 eor r7,r21 mov r0,r10 mov r10,r8 mov r8,r0 mov r0,r11 mov r11,r9 mov r9,r0 movw r18,r8 movw r20,r10 lsr r21 ror r20 ror r19 ror r18 eor r18,r8 eor r19,r9 andi r18,85 andi r19,85 eor r8,r18 eor r9,r19 mov r20,r1 mov r21,r1 lsl r18 rol r19 rol r20 rol r21 eor r8,r18 eor r9,r19 eor r10,r20 eor r11,r21 mov r0,r14 mov r14,r12 mov r12,r0 mov r0,r15 mov r15,r13 mov r13,r0 movw r18,r14 lsr r19 ror r18 eor r18,r14 eor r19,r15 andi r18,85 andi r19,85 eor r14,r18 eor r15,r19 lsl r18 rol r19 eor r14,r18 eor r15,r19 ld r18,X+ ld r19,X+ ld r20,X+ ld r21,X+ eor r4,r18 eor r5,r19 eor r6,r20 eor r7,r21 ld r18,X+ ld r19,X+ ld r20,X+ ld r21,X+ eor r8,r18 eor r9,r19 eor r10,r20 eor r11,r21 #if defined(RAMPZ) elpm r18,Z #elif defined(__AVR_HAVE_LPMX__) lpm r18,Z #elif defined(__AVR_TINY__) ld r18,Z #else lpm mov r18,r0 #endif inc r30 #if defined(RAMPZ) elpm r19,Z #elif defined(__AVR_HAVE_LPMX__) lpm r19,Z #elif defined(__AVR_TINY__) ld r19,Z #else lpm mov r19,r0 #endif inc r30 #if defined(RAMPZ) elpm r20,Z #elif defined(__AVR_HAVE_LPMX__) lpm r20,Z #elif defined(__AVR_TINY__) ld r20,Z #else lpm mov r20,r0 #endif inc r30 #if defined(RAMPZ) elpm r21,Z #elif defined(__AVR_HAVE_LPMX__) lpm r21,Z #elif defined(__AVR_TINY__) ld r21,Z #else lpm mov r21,r0 #endif inc r30 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 mov r0,r12 and r0,r8 eor r4,r0 mov r0,r13 and r0,r9 eor r5,r0 mov r0,r14 and r0,r10 eor r6,r0 mov r0,r15 and r0,r11 eor r7,r0 mov r0,r4 and r0,r22 eor r12,r0 mov r0,r5 and r0,r23 eor r13,r0 mov r0,r6 and r0,r2 eor r14,r0 mov r0,r7 and r0,r3 eor r15,r0 mov r0,r12 or r0,r4 eor r8,r0 mov r0,r13 or r0,r5 eor r9,r0 mov r0,r14 or r0,r6 eor r10,r0 mov r0,r15 or r0,r7 eor r11,r0 eor r22,r8 eor r23,r9 eor r2,r10 eor r3,r11 eor r4,r22 eor r5,r23 eor r6,r2 eor r7,r3 com r22 com r23 com r2 com r3 mov r0,r12 and r0,r4 eor r8,r0 mov r0,r13 and r0,r5 eor r9,r0 mov r0,r14 and r0,r6 eor r10,r0 mov r0,r15 and r0,r7 eor r11,r0 lsl r22 adc r22,r1 lsl r22 adc r22,r1 lsl r23 adc r23,r1 lsl r23 adc r23,r1 lsl r2 adc r2,r1 lsl r2 adc r2,r1 lsl r3 adc r3,r1 lsl r3 adc r3,r1 swap r4 swap r5 swap r6 swap r7 mov r0,r1 lsr r8 ror r0 lsr r8 ror r0 or r8,r0 mov r0,r1 lsr r9 ror r0 lsr r9 ror r0 or r9,r0 mov r0,r1 lsr r10 ror r0 lsr r10 ror r0 or r10,r0 mov r0,r1 lsr r11 ror r0 lsr r11 ror r0 or r11,r0 ld r18,X+ ld r19,X+ ld r20,X+ ld r21,X+ eor r4,r18 eor r5,r19 eor r6,r20 eor r7,r21 ld r18,X+ ld r19,X+ ld r20,X+ ld r21,X+ eor r8,r18 eor r9,r19 eor r10,r20 eor r11,r21 #if defined(RAMPZ) elpm r18,Z #elif defined(__AVR_HAVE_LPMX__) lpm r18,Z #elif defined(__AVR_TINY__) ld r18,Z #else lpm mov r18,r0 #endif inc r30 #if defined(RAMPZ) elpm r19,Z #elif defined(__AVR_HAVE_LPMX__) lpm r19,Z #elif defined(__AVR_TINY__) ld r19,Z #else lpm mov r19,r0 #endif inc r30 #if defined(RAMPZ) elpm r20,Z #elif defined(__AVR_HAVE_LPMX__) lpm r20,Z #elif defined(__AVR_TINY__) ld r20,Z #else lpm mov r20,r0 #endif inc r30 #if defined(RAMPZ) elpm r21,Z #elif defined(__AVR_HAVE_LPMX__) lpm r21,Z #elif defined(__AVR_TINY__) ld r21,Z #else lpm mov r21,r0 #endif inc r30 eor r12,r18 eor r13,r19 eor r14,r20 eor r15,r21 mov r0,r22 and r0,r8 eor r4,r0 mov r0,r23 and r0,r9 eor r5,r0 mov r0,r2 and r0,r10 eor r6,r0 mov r0,r3 and r0,r11 eor r7,r0 mov r0,r4 and r0,r12 eor r22,r0 mov r0,r5 and r0,r13 eor r23,r0 mov r0,r6 and r0,r14 eor r2,r0 mov r0,r7 and r0,r15 eor r3,r0 mov r0,r22 or r0,r4 eor r8,r0 mov r0,r23 or r0,r5 eor r9,r0 mov r0,r2 or r0,r6 eor r10,r0 mov r0,r3 or r0,r7 eor r11,r0 eor r12,r8 eor r13,r9 eor r14,r10 eor r15,r11 eor r4,r12 eor r5,r13 eor r6,r14 eor r7,r15 com r12 com r13 com r14 com r15 mov r0,r22 and r0,r4 eor r8,r0 mov r0,r23 and r0,r5 eor r9,r0 mov r0,r2 and r0,r6 eor r10,r0 mov r0,r3 and r0,r7 eor r11,r0 mov r0,r6 mov r6,r4 mov r4,r0 mov r0,r7 mov r7,r5 mov r5,r0 mov r0,r8 mov r8,r9 mov r9,r10 mov r10,r11 mov r11,r0 mov r0,r15 mov r15,r14 mov r14,r13 mov r13,r12 mov r12,r0 ld r18,X+ ld r19,X+ ld r20,X+ ld r21,X+ eor r4,r18 eor r5,r19 eor r6,r20 eor r7,r21 ld r18,X+ ld r19,X+ ld r20,X+ ld r21,X+ eor r8,r18 eor r9,r19 eor r10,r20 eor r11,r21 #if defined(RAMPZ) elpm r18,Z #elif defined(__AVR_HAVE_LPMX__) lpm r18,Z #elif defined(__AVR_TINY__) ld r18,Z #else lpm mov r18,r0 #endif inc r30 #if defined(RAMPZ) elpm r19,Z #elif defined(__AVR_HAVE_LPMX__) lpm r19,Z #elif defined(__AVR_TINY__) ld r19,Z #else lpm mov r19,r0 #endif inc r30 #if defined(RAMPZ) elpm r20,Z #elif defined(__AVR_HAVE_LPMX__) lpm r20,Z #elif defined(__AVR_TINY__) ld r20,Z #else lpm mov r20,r0 #endif inc r30 #if defined(RAMPZ) elpm r21,Z #elif defined(__AVR_HAVE_LPMX__) lpm r21,Z #elif defined(__AVR_TINY__) ld r21,Z #else lpm mov r21,r0 #endif inc r30 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 eor r22,r12 eor r23,r13 eor r2,r14 eor r3,r15 eor r12,r22 eor r13,r23 eor r14,r2 eor r15,r3 eor r22,r12 eor r23,r13 eor r2,r14 eor r3,r15 ret 2067: movw r30,r26 sbiw r30,40 push r3 push r2 push r23 push r22 push r7 push r6 push r5 push r4 ld r22,Z ldd r23,Z+1 ldd r2,Z+2 ldd r3,Z+3 ldd r26,Z+4 ldd r27,Z+5 ldd r24,Z+6 ldd r25,Z+7 movw r18,r26 movw r20,r24 movw r18,r20 mov r20,r1 mov r21,r1 eor r18,r26 eor r19,r27 andi r18,51 andi r19,51 eor r26,r18 eor r27,r19 mov r20,r1 mov r21,r1 movw r20,r18 mov r18,r1 mov r19,r1 eor r26,r18 eor r27,r19 eor r24,r20 eor r25,r21 movw r18,r26 movw r20,r24 lsr r21 ror r20 ror r19 ror r18 eor r18,r26 eor r19,r27 eor r20,r24 eor r21,r25 andi r18,68 andi r19,68 andi r20,85 andi r21,85 eor r26,r18 eor r27,r19 eor r24,r20 eor r25,r21 lsl r18 rol r19 rol r20 rol r21 eor r26,r18 eor r27,r19 eor r24,r20 eor r25,r21 st Z,r26 std Z+1,r27 std Z+2,r24 std Z+3,r25 movw r18,r22 movw r20,r2 andi r18,51 andi r19,51 andi r20,51 andi r21,51 andi r22,204 andi r23,204 ldi r17,204 and r2,r17 and r3,r17 or r2,r21 or r3,r18 or r22,r19 or r23,r20 movw r18,r2 movw r20,r22 lsr r21 ror r20 ror r19 ror r18 eor r18,r2 eor r19,r3 eor r20,r22 eor r21,r23 mov r18,r1 andi r19,17 andi r20,85 andi r21,85 eor r2,r18 eor r3,r19 eor r22,r20 eor r23,r21 lsl r18 rol r19 rol r20 rol r21 eor r2,r18 eor r3,r19 eor r22,r20 eor r23,r21 std Z+4,r2 std Z+5,r3 std Z+6,r22 std Z+7,r23 ldd r22,Z+8 ldd r23,Z+9 ldd r2,Z+10 ldd r3,Z+11 ldd r26,Z+12 ldd r27,Z+13 ldd r24,Z+14 ldd r25,Z+15 lsl r26 adc r26,r1 lsl r26 adc r26,r1 swap r27 lsl r24 adc r24,r1 lsl r24 adc r24,r1 swap r25 std Z+8,r26 std Z+9,r27 std Z+10,r24 std Z+11,r25 lsl r22 adc r22,r1 lsl r22 adc r22,r1 lsl r22 adc r22,r1 lsl r23 adc r23,r1 lsl r23 adc r23,r1 lsl r2 adc r2,r1 lsl r2 adc r2,r1 lsl r2 adc r2,r1 lsl r3 adc r3,r1 lsl r3 adc r3,r1 std Z+12,r22 std Z+13,r23 std Z+14,r2 std Z+15,r3 ldd r22,Z+16 ldd r23,Z+17 ldd r2,Z+18 ldd r3,Z+19 ldd r26,Z+20 ldd r27,Z+21 ldd r24,Z+22 ldd r25,Z+23 movw r18,r26 movw r20,r24 andi r18,170 andi r19,170 andi r20,170 andi r21,170 andi r26,85 andi r27,85 andi r24,85 andi r25,85 or r26,r19 or r27,r20 or r24,r21 or r25,r18 std Z+16,r24 std Z+17,r25 std Z+18,r26 std Z+19,r27 movw r18,r22 movw r20,r2 andi r18,85 andi r19,85 andi r20,85 andi r21,85 andi r22,170 andi r23,170 ldi r16,170 and r2,r16 and r3,r16 lsl r22 rol r23 rol r2 rol r3 adc r22,r1 lsl r22 rol r23 rol r2 rol r3 adc r22,r1 lsl r22 rol r23 rol r2 rol r3 adc r22,r1 lsl r22 rol r23 rol r2 rol r3 adc r22,r1 or r22,r18 or r23,r19 or r2,r20 or r3,r21 std Z+20,r3 std Z+21,r22 std Z+22,r23 std Z+23,r2 ldd r22,Z+24 ldd r23,Z+25 ldd r2,Z+26 ldd r3,Z+27 ldd r26,Z+28 ldd r27,Z+29 ldd r24,Z+30 ldd r25,Z+31 movw r18,r26 movw r20,r24 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 eor r18,r26 eor r19,r27 eor r20,r24 eor r21,r25 andi r18,3 andi r19,3 andi r20,3 andi r21,3 eor r26,r18 eor r27,r19 eor r24,r20 eor r25,r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 eor r26,r18 eor r27,r19 eor r24,r20 eor r25,r21 movw r18,r26 movw r20,r24 lsr r21 ror r20 ror r19 ror r18 andi r18,120 andi r19,120 andi r20,120 andi r21,120 movw r4,r18 movw r6,r20 lsr r7 ror r6 ror r5 ror r4 lsr r7 ror r6 ror r5 ror r4 lsr r7 ror r6 ror r5 ror r4 lsr r7 ror r6 ror r5 ror r4 eor r4,r18 eor r5,r19 eor r6,r20 eor r7,r21 ldi r16,8 and r4,r16 and r5,r16 and r6,r16 and r7,r16 eor r18,r4 eor r19,r5 eor r20,r6 eor r21,r7 lsl r4 rol r5 rol r6 rol r7 lsl r4 rol r5 rol r6 rol r7 lsl r4 rol r5 rol r6 rol r7 lsl r4 rol r5 rol r6 rol r7 eor r18,r4 eor r19,r5 eor r20,r6 eor r21,r7 andi r26,15 andi r27,15 andi r24,15 andi r25,15 or r26,r18 or r27,r19 or r24,r20 or r25,r21 std Z+24,r26 std Z+25,r27 std Z+26,r24 std Z+27,r25 movw r18,r2 lsr r19 ror r18 lsr r19 ror r18 andi r18,48 andi r19,48 movw r26,r22 movw r24,r2 andi r26,1 andi r27,1 andi r24,1 andi r25,1 lsl r26 rol r27 rol r24 rol r25 lsl r26 rol r27 rol r24 rol r25 lsl r26 rol r27 rol r24 rol r25 or r26,r18 or r27,r19 movw r18,r2 lsl r18 rol r19 lsl r18 rol r19 andi r18,192 andi r19,192 or r26,r18 or r27,r19 movw r18,r22 andi r18,224 andi r19,224 lsr r19 ror r18 or r24,r18 or r25,r19 movw r18,r22 movw r20,r2 lsr r21 ror r20 ror r19 ror r18 andi r18,7 andi r19,7 andi r20,7 andi r21,7 or r26,r18 or r27,r19 or r24,r20 or r25,r21 andi r22,16 andi r23,16 lsl r22 rol r23 lsl r22 rol r23 lsl r22 rol r23 or r24,r22 or r25,r23 std Z+28,r26 std Z+29,r27 std Z+30,r24 std Z+31,r25 ldd r22,Z+32 ldd r23,Z+33 ldd r2,Z+34 ldd r3,Z+35 ldd r26,Z+36 ldd r27,Z+37 ldd r24,Z+38 ldd r25,Z+39 mov r0,r1 lsr r25 ror r24 ror r0 lsr r25 ror r24 ror r0 lsr r25 ror r24 ror r0 lsr r25 ror r24 ror r0 or r25,r0 std Z+32,r27 std Z+33,r26 std Z+34,r24 std Z+35,r25 mov r0,r1 lsr r23 ror r22 ror r0 lsr r23 ror r22 ror r0 lsr r23 ror r22 ror r0 lsr r23 ror r22 ror r0 or r23,r0 mov r0,r2 mov r2,r3 mov r3,r0 lsl r2 rol r3 adc r2,r1 lsl r2 rol r3 adc r2,r1 std Z+36,r22 std Z+37,r23 std Z+38,r2 std Z+39,r3 pop r4 pop r5 pop r6 pop r7 pop r22 pop r23 pop r2 pop r3 movw r26,r30 ret 2541: #if defined(RAMPZ) pop r0 out _SFR_IO_ADDR(RAMPZ),r0 #endif subi r28,175 sbci r29,255 ld r26,Y+ ld r27,Y subi r28,82 sbc r29,r1 st X+,r22 st X+,r23 st X+,r2 st X+,r3 st X+,r4 st X+,r5 st X+,r6 st X+,r7 st X+,r8 st X+,r9 st X+,r10 st X+,r11 st X+,r12 st X+,r13 st X+,r14 st X+,r15 subi r28,174 sbci r29,255 in r0,0x3f cli out 0x3e,r29 out 0x3f,r0 out 0x3d,r28 pop r17 pop r16 pop r15 pop r14 pop r13 pop r12 pop r11 pop r10 pop r9 pop r8 pop r7 pop r6 pop r5 pop r4 pop r3 pop r2 pop r29 pop r28 ret .size gift128b_encrypt_preloaded, .-gift128b_encrypt_preloaded .section .progmem.data,"a",@progbits .p2align 8 .type table_1, @object .size table_1, 40 table_1: .byte 1 .byte 3 .byte 7 .byte 15 .byte 31 .byte 62 .byte 61 .byte 59 .byte 55 .byte 47 .byte 30 .byte 60 .byte 57 .byte 51 .byte 39 .byte 14 .byte 29 .byte 58 .byte 53 .byte 43 .byte 22 .byte 44 .byte 24 .byte 48 .byte 33 .byte 2 .byte 5 .byte 11 .byte 23 .byte 46 .byte 28 .byte 56 .byte 49 .byte 35 .byte 6 .byte 13 .byte 27 .byte 54 .byte 45 .byte 26 .text .global gift128b_decrypt .type gift128b_decrypt, @function gift128b_decrypt: push r28 push r29 push r2 push r3 push r4 push r5 push r6 push r7 push r8 push r9 push r10 push r11 push r12 push r13 push r14 push r15 push r16 push r23 push r22 movw r30,r24 movw r26,r20 in r28,0x3d in r29,0x3e sbiw r28,16 in r0,0x3f cli out 0x3e,r29 out 0x3f,r0 out 0x3d,r28 .L__stack_usage = 35 ld r3,X+ ld r2,X+ ld r23,X+ ld r22,X+ ld r7,X+ ld r6,X+ ld r5,X+ ld r4,X+ ld r11,X+ ld r10,X+ ld r9,X+ ld r8,X+ ld r15,X+ ld r14,X+ ld r13,X+ ld r12,X+ ldd r26,Z+12 ldd r27,Z+13 ldd r24,Z+14 ldd r25,Z+15 mov r0,r27 mov r27,r26 mov r26,r0 mov r0,r1 lsr r25 ror r24 ror r0 lsr r25 ror r24 ror r0 lsr r25 ror r24 ror r0 lsr r25 ror r24 ror r0 or r25,r0 std Y+1,r26 std Y+2,r27 std Y+3,r24 std Y+4,r25 ldd r26,Z+4 ldd r27,Z+5 ldd r24,Z+6 ldd r25,Z+7 mov r0,r27 mov r27,r26 mov r26,r0 mov r0,r1 lsr r25 ror r24 ror r0 lsr r25 ror r24 ror r0 lsr r25 ror r24 ror r0 lsr r25 ror r24 ror r0 or r25,r0 std Y+5,r26 std Y+6,r27 std Y+7,r24 std Y+8,r25 ldd r26,Z+8 ldd r27,Z+9 ldd r24,Z+10 ldd r25,Z+11 mov r0,r27 mov r27,r26 mov r26,r0 mov r0,r1 lsr r25 ror r24 ror r0 lsr r25 ror r24 ror r0 lsr r25 ror r24 ror r0 lsr r25 ror r24 ror r0 or r25,r0 std Y+9,r26 std Y+10,r27 std Y+11,r24 std Y+12,r25 ld r26,Z ldd r27,Z+1 ldd r24,Z+2 ldd r25,Z+3 mov r0,r27 mov r27,r26 mov r26,r0 mov r0,r1 lsr r25 ror r24 ror r0 lsr r25 ror r24 ror r0 lsr r25 ror r24 ror r0 lsr r25 ror r24 ror r0 or r25,r0 ldi r30,lo8(table_1) ldi r31,hi8(table_1) #if defined(RAMPZ) ldi r17,hh8(table_1) in r0,_SFR_IO_ADDR(RAMPZ) push r0 out _SFR_IO_ADDR(RAMPZ),r17 #endif ldi r16,40 114: ldd r0,Y+9 eor r8,r0 ldd r0,Y+10 eor r9,r0 ldd r0,Y+11 eor r10,r0 ldd r0,Y+12 eor r11,r0 std Y+13,r26 std Y+14,r27 std Y+15,r24 std Y+16,r25 ldd r26,Y+1 ldd r27,Y+2 ldd r24,Y+3 ldd r25,Y+4 mov r0,r1 lsr r27 ror r26 ror r0 lsr r27 ror r26 ror r0 lsr r27 ror r26 ror r0 lsr r27 ror r26 ror r0 or r27,r0 lsl r24 rol r25 adc r24,r1 lsl r24 rol r25 adc r24,r1 rcall 266f ldd r0,Y+13 eor r8,r0 ldd r0,Y+14 eor r9,r0 ldd r0,Y+15 eor r10,r0 ldd r0,Y+16 eor r11,r0 std Y+1,r26 std Y+2,r27 std Y+3,r24 std Y+4,r25 ldd r26,Y+5 ldd r27,Y+6 ldd r24,Y+7 ldd r25,Y+8 mov r0,r1 lsr r27 ror r26 ror r0 lsr r27 ror r26 ror r0 lsr r27 ror r26 ror r0 lsr r27 ror r26 ror r0 or r27,r0 lsl r24 rol r25 adc r24,r1 lsl r24 rol r25 adc r24,r1 rcall 266f ldd r0,Y+1 eor r8,r0 ldd r0,Y+2 eor r9,r0 ldd r0,Y+3 eor r10,r0 ldd r0,Y+4 eor r11,r0 std Y+5,r26 std Y+6,r27 std Y+7,r24 std Y+8,r25 ldd r26,Y+9 ldd r27,Y+10 ldd r24,Y+11 ldd r25,Y+12 mov r0,r1 lsr r27 ror r26 ror r0 lsr r27 ror r26 ror r0 lsr r27 ror r26 ror r0 lsr r27 ror r26 ror r0 or r27,r0 lsl r24 rol r25 adc r24,r1 lsl r24 rol r25 adc r24,r1 rcall 266f ldd r0,Y+5 eor r8,r0 ldd r0,Y+6 eor r9,r0 ldd r0,Y+7 eor r10,r0 ldd r0,Y+8 eor r11,r0 std Y+9,r26 std Y+10,r27 std Y+11,r24 std Y+12,r25 ldd r26,Y+13 ldd r27,Y+14 ldd r24,Y+15 ldd r25,Y+16 mov r0,r1 lsr r27 ror r26 ror r0 lsr r27 ror r26 ror r0 lsr r27 ror r26 ror r0 lsr r27 ror r26 ror r0 or r27,r0 lsl r24 rol r25 adc r24,r1 lsl r24 rol r25 adc r24,r1 rcall 266f cpse r16,r1 rjmp 114b rjmp 611f 266: eor r4,r26 eor r5,r27 eor r6,r24 eor r7,r25 ldi r18,128 eor r15,r18 dec r16 mov r30,r16 #if defined(RAMPZ) elpm r18,Z #elif defined(__AVR_HAVE_LPMX__) lpm r18,Z #elif defined(__AVR_TINY__) ld r18,Z #else lpm mov r18,r0 #endif eor r12,r18 bst r22,1 bld r0,0 bst r3,0 bld r22,1 bst r22,6 bld r3,0 bst r2,1 bld r22,6 bst r3,4 bld r2,1 bst r22,7 bld r3,4 bst r23,1 bld r22,7 bst r3,2 bld r23,1 bst r2,6 bld r3,2 bst r2,5 bld r2,6 bst r3,5 bld r2,5 bst r3,7 bld r3,5 bst r23,7 bld r3,7 bst r23,3 bld r23,7 bst r23,2 bld r23,3 bst r2,2 bld r23,2 bst r2,4 bld r2,2 bst r22,5 bld r2,4 bst r3,1 bld r22,5 bst r3,6 bld r3,1 bst r2,7 bld r3,6 bst r23,5 bld r2,7 bst r3,3 bld r23,5 bst r23,6 bld r3,3 bst r2,3 bld r23,6 bst r23,4 bld r2,3 bst r22,3 bld r23,4 bst r23,0 bld r22,3 bst r22,2 bld r23,0 bst r2,0 bld r22,2 bst r22,4 bld r2,0 bst r0,0 bld r22,4 bst r4,0 bld r0,0 bst r5,0 bld r4,0 bst r5,2 bld r5,0 bst r7,2 bld r5,2 bst r7,6 bld r7,2 bst r7,7 bld r7,6 bst r6,7 bld r7,7 bst r6,5 bld r6,7 bst r4,5 bld r6,5 bst r4,1 bld r4,5 bst r0,0 bld r4,1 bst r4,2 bld r0,0 bst r7,0 bld r4,2 bst r5,6 bld r7,0 bst r7,3 bld r5,6 bst r6,6 bld r7,3 bst r7,5 bld r6,6 bst r4,7 bld r7,5 bst r6,1 bld r4,7 bst r4,4 bld r6,1 bst r5,1 bld r4,4 bst r0,0 bld r5,1 bst r4,3 bld r0,0 bst r6,0 bld r4,3 bst r5,4 bld r6,0 bst r5,3 bld r5,4 bst r6,2 bld r5,3 bst r7,4 bld r6,2 bst r5,7 bld r7,4 bst r6,3 bld r5,7 bst r6,4 bld r6,3 bst r5,5 bld r6,4 bst r0,0 bld r5,5 bst r4,6 bld r0,0 bst r7,1 bld r4,6 bst r0,0 bld r7,1 bst r8,0 bld r0,0 bst r10,0 bld r8,0 bst r10,4 bld r10,0 bst r10,5 bld r10,4 bst r9,5 bld r10,5 bst r9,3 bld r9,5 bst r11,2 bld r9,3 bst r8,6 bld r11,2 bst r8,1 bld r8,6 bst r9,0 bld r8,1 bst r10,2 bld r9,0 bst r8,4 bld r10,2 bst r10,1 bld r8,4 bst r9,4 bld r10,1 bst r10,3 bld r9,4 bst r11,4 bld r10,3 bst r10,7 bld r11,4 bst r11,5 bld r10,7 bst r9,7 bld r11,5 bst r11,3 bld r9,7 bst r11,6 bld r11,3 bst r8,7 bld r11,6 bst r11,1 bld r8,7 bst r9,6 bld r11,1 bst r8,3 bld r9,6 bst r11,0 bld r8,3 bst r10,6 bld r11,0 bst r8,5 bld r10,6 bst r9,1 bld r8,5 bst r9,2 bld r9,1 bst r8,2 bld r9,2 bst r0,0 bld r8,2 bst r12,0 bld r0,0 bst r15,0 bld r12,0 bst r15,6 bld r15,0 bst r13,7 bld r15,6 bst r12,3 bld r13,7 bst r0,0 bld r12,3 bst r12,1 bld r0,0 bst r14,0 bld r12,1 bst r15,4 bld r14,0 bst r15,7 bld r15,4 bst r12,7 bld r15,7 bst r0,0 bld r12,7 bst r12,2 bld r0,0 bst r13,0 bld r12,2 bst r15,2 bld r13,0 bst r13,6 bld r15,2 bst r13,3 bld r13,6 bst r0,0 bld r13,3 bst r12,4 bld r0,0 bst r15,1 bld r12,4 bst r14,6 bld r15,1 bst r13,5 bld r14,6 bst r14,3 bld r13,5 bst r0,0 bld r14,3 bst r12,5 bld r0,0 bst r14,1 bld r12,5 bst r14,4 bld r14,1 bst r15,5 bld r14,4 bst r14,7 bld r15,5 bst r0,0 bld r14,7 bst r12,6 bld r0,0 bst r13,1 bld r12,6 bst r14,2 bld r13,1 bst r13,4 bld r14,2 bst r15,3 bld r13,4 bst r0,0 bld r15,3 movw r18,r12 movw r20,r14 movw r12,r22 movw r14,r2 movw r22,r18 movw r2,r20 and r18,r4 and r19,r5 and r20,r6 and r21,r7 eor r8,r18 eor r9,r19 eor r10,r20 eor r11,r21 com r12 com r13 com r14 com r15 eor r4,r12 eor r5,r13 eor r6,r14 eor r7,r15 eor r12,r8 eor r13,r9 eor r14,r10 eor r15,r11 mov r0,r22 or r0,r4 eor r8,r0 mov r0,r23 or r0,r5 eor r9,r0 mov r0,r2 or r0,r6 eor r10,r0 mov r0,r3 or r0,r7 eor r11,r0 mov r0,r4 and r0,r12 eor r22,r0 mov r0,r5 and r0,r13 eor r23,r0 mov r0,r6 and r0,r14 eor r2,r0 mov r0,r7 and r0,r15 eor r3,r0 mov r0,r22 and r0,r8 eor r4,r0 mov r0,r23 and r0,r9 eor r5,r0 mov r0,r2 and r0,r10 eor r6,r0 mov r0,r3 and r0,r11 eor r7,r0 ret 611: #if defined(RAMPZ) pop r0 out _SFR_IO_ADDR(RAMPZ),r0 #endif ldd r26,Y+17 ldd r27,Y+18 st X+,r3 st X+,r2 st X+,r23 st X+,r22 st X+,r7 st X+,r6 st X+,r5 st X+,r4 st X+,r11 st X+,r10 st X+,r9 st X+,r8 st X+,r15 st X+,r14 st X+,r13 st X+,r12 adiw r28,18 in r0,0x3f cli out 0x3e,r29 out 0x3f,r0 out 0x3d,r28 pop r16 pop r15 pop r14 pop r13 pop r12 pop r11 pop r10 pop r9 pop r8 pop r7 pop r6 pop r5 pop r4 pop r3 pop r2 pop r29 pop r28 ret .size gift128b_decrypt, .-gift128b_decrypt #endif #endif