**** Line 64 (old) / 64 (new) ****

  Description:
    Moved ED to the list of generics

  Change:
    ; ED     : std_logic_vector(0 to 1) := "11"  -- Encryption | Decryption      



**** Line 69 (old) / 69 (new) ****

  Description:
    Removed ED signal declaration



**** Line 107,108 (old) / 106,108 (new) ****

  Description:
    Added new signal declarations to delay primary inputs after clock edge

  Change:
    signal i_dom_sep_buf : domsep_ty;
    signal i_mode_buf    : mode_ty;



**** Line 113 (old) / 114 - 122 (new) ****

  Description:
    added new processes to delay a change in primary inputs after clock edge

  Change:
    i_dom_sep_proc : process(i_dom_sep_buf)
    begin
      i_dom_sep <= i_dom_sep_buf after hold;
    end process;

    i_mode_proc : process(i_mode_buf)
    begin
      i_mode <= i_mode_buf after hold;
    end process;



**** Line 202 (old) / 211 (new) ****
**** Line 233 (old) / 242 (new) ****
**** Line 241 (old) / 250 (new) ****
**** Line 250 (old) / 259 (new) ****
**** Line 299 (old) / 309 (new) ****
**** Line 330 (old) / 340 (new) ****
**** Line 338 (old) / 348 (new) ****
**** Line 347 (old) / 357 (new) ****

   Description:
     changed signal name
 
   Change:
     was
       i_dom_sep
     now
       i_dom_sep_buf



**** Line 242 (old) / 251 (new) ****
**** Line 339 (old) / 349 (new) ****

   Description:
     changed signal name

   Change:
     was
       i_mode
     now
       i_mode_buf	   



**** Line 212 (old) / 221 (new) ****
**** Line 309 (old) / 319 (new) ****

  Description:
    different wait statement

  Change:
    was
      wait for load_delay;
    now
      wait until rising_edge(clk);



**** Line 256 (old) / 265 (new) ****
**** Line 353 (old) / 363 (new) ****

  Description:
    This particular change was necessary for a correct tag extraction. Most hold statements are now in wage_unsynth.vhd

  Change:
    removed
      wait for hold;