#if defined(__AVR__)
#include <avr/io.h>
/* Automatically generated - do not edit */

	.section	.progmem.data,"a",@progbits
	.p2align	8
	.type	table_0, @object
	.size	table_0, 96
table_0:
	.byte	7
	.byte	83
	.byte	67
	.byte	80
	.byte	40
	.byte	20
	.byte	10
	.byte	93
	.byte	228
	.byte	92
	.byte	174
	.byte	87
	.byte	155
	.byte	73
	.byte	94
	.byte	145
	.byte	72
	.byte	36
	.byte	224
	.byte	127
	.byte	204
	.byte	141
	.byte	198
	.byte	99
	.byte	209
	.byte	190
	.byte	50
	.byte	83
	.byte	169
	.byte	84
	.byte	26
	.byte	29
	.byte	78
	.byte	96
	.byte	48
	.byte	24
	.byte	34
	.byte	40
	.byte	117
	.byte	104
	.byte	52
	.byte	154
	.byte	247
	.byte	108
	.byte	37
	.byte	225
	.byte	112
	.byte	56
	.byte	98
	.byte	130
	.byte	253
	.byte	246
	.byte	123
	.byte	189
	.byte	150
	.byte	71
	.byte	249
	.byte	157
	.byte	206
	.byte	103
	.byte	113
	.byte	107
	.byte	118
	.byte	64
	.byte	32
	.byte	16
	.byte	170
	.byte	136
	.byte	160
	.byte	79
	.byte	39
	.byte	19
	.byte	43
	.byte	220
	.byte	176
	.byte	190
	.byte	95
	.byte	47
	.byte	233
	.byte	139
	.byte	9
	.byte	91
	.byte	173
	.byte	214
	.byte	207
	.byte	89
	.byte	30
	.byte	233
	.byte	116
	.byte	186
	.byte	183
	.byte	198
	.byte	173
	.byte	127
	.byte	63
	.byte	31

	.text
.global sliscp_light320_permute
	.type sliscp_light320_permute, @function
sliscp_light320_permute:
	push r28
	push r29
	push r2
	push r3
	push r4
	push r5
	push r6
	push r7
	push r8
	push r9
	push r10
	push r11
	push r12
	push r13
	push r14
	push r15
	push r16
	push r17
	movw r30,r24
	in r28,0x3d
	in r29,0x3e
	sbiw r28,16
	in r0,0x3f
	cli
	out 0x3e,r29
	out 0x3f,r0
	out 0x3d,r28
.L__stack_usage = 34
	ldd r21,Z+8
	ldd r20,Z+9
	ldd r19,Z+10
	ldd r18,Z+11
	ldd r27,Z+12
	ldd r26,Z+13
	ldd r23,Z+14
	ldd r22,Z+15
	ldd r5,Z+24
	ldd r4,Z+25
	ldd r3,Z+26
	ldd r2,Z+27
	ldd r9,Z+28
	ldd r8,Z+29
	ldd r7,Z+30
	ldd r6,Z+31
	std Y+1,r18
	std Y+2,r19
	std Y+3,r20
	std Y+4,r21
	std Y+5,r22
	std Y+6,r23
	std Y+7,r26
	std Y+8,r27
	std Y+9,r2
	std Y+10,r3
	std Y+11,r4
	std Y+12,r5
	std Y+13,r6
	std Y+14,r7
	std Y+15,r8
	std Y+16,r9
	ld r21,Z
	ldd r20,Z+1
	ldd r19,Z+2
	ldd r18,Z+3
	ldd r27,Z+16
	ldd r26,Z+17
	ldd r23,Z+18
	ldd r22,Z+19
	ldd r5,Z+4
	ldd r4,Z+5
	ldd r3,Z+6
	ldd r2,Z+7
	ldd r9,Z+20
	ldd r8,Z+21
	ldd r7,Z+22
	ldd r6,Z+23
	ldd r13,Z+32
	ldd r12,Z+33
	ldd r11,Z+34
	ldd r10,Z+35
	ldd r25,Z+36
	ldd r24,Z+37
	ldd r15,Z+38
	ldd r14,Z+39
	push r31
	push r30
	ldi r30,lo8(table_0)
	ldi r31,hi8(table_0)
#if defined(RAMPZ)
	ldi r16,hh8(table_0)
	in r0,_SFR_IO_ADDR(RAMPZ)
	push r0
	out _SFR_IO_ADDR(RAMPZ),r16
#endif
	ldi r30,0
60:
#if defined(RAMPZ)
	elpm r16,Z
#elif defined(__AVR_HAVE_LPMX__)
	lpm r16,Z
#elif defined(__AVR_TINY__)
	ld r16,Z
#else
	lpm
	mov r16,r0
#endif
	inc r30
	push r30
	mov r30,r16
	movw r16,r18
	mov r1,r20
	mov r0,r21
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	eor r22,r16
	eor r23,r17
	eor r26,r1
	eor r27,r0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	and r16,r18
	and r17,r19
	and r1,r20
	and r0,r21
	eor r22,r16
	eor r23,r17
	eor r26,r1
	eor r27,r0
	com r23
	com r26
	com r27
	ldi r16,255
	lsr r30
	rol r16
	eor r22,r16
	movw r16,r22
	mov r1,r26
	mov r0,r27
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	eor r18,r16
	eor r19,r17
	eor r20,r1
	eor r21,r0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	and r16,r22
	and r17,r23
	and r1,r26
	and r0,r27
	eor r18,r16
	eor r19,r17
	eor r20,r1
	eor r21,r0
	com r19
	com r20
	com r21
	ldi r16,255
	lsr r30
	rol r16
	eor r18,r16
	movw r16,r18
	mov r1,r20
	mov r0,r21
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	eor r22,r16
	eor r23,r17
	eor r26,r1
	eor r27,r0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	and r16,r18
	and r17,r19
	and r1,r20
	and r0,r21
	eor r22,r16
	eor r23,r17
	eor r26,r1
	eor r27,r0
	com r23
	com r26
	com r27
	ldi r16,255
	lsr r30
	rol r16
	eor r22,r16
	movw r16,r22
	mov r1,r26
	mov r0,r27
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	eor r18,r16
	eor r19,r17
	eor r20,r1
	eor r21,r0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	and r16,r22
	and r17,r23
	and r1,r26
	and r0,r27
	eor r18,r16
	eor r19,r17
	eor r20,r1
	eor r21,r0
	com r19
	com r20
	com r21
	ldi r16,255
	lsr r30
	rol r16
	eor r18,r16
	movw r16,r18
	mov r1,r20
	mov r0,r21
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	eor r22,r16
	eor r23,r17
	eor r26,r1
	eor r27,r0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	and r16,r18
	and r17,r19
	and r1,r20
	and r0,r21
	eor r22,r16
	eor r23,r17
	eor r26,r1
	eor r27,r0
	com r23
	com r26
	com r27
	ldi r16,255
	lsr r30
	rol r16
	eor r22,r16
	movw r16,r22
	mov r1,r26
	mov r0,r27
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	eor r18,r16
	eor r19,r17
	eor r20,r1
	eor r21,r0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	and r16,r22
	and r17,r23
	and r1,r26
	and r0,r27
	eor r18,r16
	eor r19,r17
	eor r20,r1
	eor r21,r0
	com r19
	com r20
	com r21
	ldi r16,255
	lsr r30
	rol r16
	eor r18,r16
	movw r16,r18
	mov r1,r20
	mov r0,r21
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	eor r22,r16
	eor r23,r17
	eor r26,r1
	eor r27,r0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	and r16,r18
	and r17,r19
	and r1,r20
	and r0,r21
	eor r22,r16
	eor r23,r17
	eor r26,r1
	eor r27,r0
	com r23
	com r26
	com r27
	ldi r16,255
	lsr r30
	rol r16
	eor r22,r16
	movw r16,r22
	mov r1,r26
	mov r0,r27
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	eor r18,r16
	eor r19,r17
	eor r20,r1
	eor r21,r0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	and r16,r22
	and r17,r23
	and r1,r26
	and r0,r27
	eor r18,r16
	eor r19,r17
	eor r20,r1
	eor r21,r0
	com r19
	com r20
	com r21
	ldi r16,255
	lsr r30
	rol r16
	eor r18,r16
	pop r30
#if defined(RAMPZ)
	elpm r16,Z
#elif defined(__AVR_HAVE_LPMX__)
	lpm r16,Z
#elif defined(__AVR_TINY__)
	ld r16,Z
#else
	lpm
	mov r16,r0
#endif
	inc r30
	push r30
	mov r30,r16
	movw r16,r2
	mov r1,r4
	mov r0,r5
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	eor r6,r16
	eor r7,r17
	eor r8,r1
	eor r9,r0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	and r16,r2
	and r17,r3
	and r1,r4
	and r0,r5
	eor r6,r16
	eor r7,r17
	eor r8,r1
	eor r9,r0
	com r7
	com r8
	com r9
	ldi r16,255
	lsr r30
	rol r16
	eor r6,r16
	movw r16,r6
	mov r1,r8
	mov r0,r9
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	eor r2,r16
	eor r3,r17
	eor r4,r1
	eor r5,r0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	and r16,r6
	and r17,r7
	and r1,r8
	and r0,r9
	eor r2,r16
	eor r3,r17
	eor r4,r1
	eor r5,r0
	com r3
	com r4
	com r5
	ldi r16,255
	lsr r30
	rol r16
	eor r2,r16
	movw r16,r2
	mov r1,r4
	mov r0,r5
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	eor r6,r16
	eor r7,r17
	eor r8,r1
	eor r9,r0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	and r16,r2
	and r17,r3
	and r1,r4
	and r0,r5
	eor r6,r16
	eor r7,r17
	eor r8,r1
	eor r9,r0
	com r7
	com r8
	com r9
	ldi r16,255
	lsr r30
	rol r16
	eor r6,r16
	movw r16,r6
	mov r1,r8
	mov r0,r9
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	eor r2,r16
	eor r3,r17
	eor r4,r1
	eor r5,r0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	and r16,r6
	and r17,r7
	and r1,r8
	and r0,r9
	eor r2,r16
	eor r3,r17
	eor r4,r1
	eor r5,r0
	com r3
	com r4
	com r5
	ldi r16,255
	lsr r30
	rol r16
	eor r2,r16
	movw r16,r2
	mov r1,r4
	mov r0,r5
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	eor r6,r16
	eor r7,r17
	eor r8,r1
	eor r9,r0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	and r16,r2
	and r17,r3
	and r1,r4
	and r0,r5
	eor r6,r16
	eor r7,r17
	eor r8,r1
	eor r9,r0
	com r7
	com r8
	com r9
	ldi r16,255
	lsr r30
	rol r16
	eor r6,r16
	movw r16,r6
	mov r1,r8
	mov r0,r9
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	eor r2,r16
	eor r3,r17
	eor r4,r1
	eor r5,r0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	and r16,r6
	and r17,r7
	and r1,r8
	and r0,r9
	eor r2,r16
	eor r3,r17
	eor r4,r1
	eor r5,r0
	com r3
	com r4
	com r5
	ldi r16,255
	lsr r30
	rol r16
	eor r2,r16
	movw r16,r2
	mov r1,r4
	mov r0,r5
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	eor r6,r16
	eor r7,r17
	eor r8,r1
	eor r9,r0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	and r16,r2
	and r17,r3
	and r1,r4
	and r0,r5
	eor r6,r16
	eor r7,r17
	eor r8,r1
	eor r9,r0
	com r7
	com r8
	com r9
	ldi r16,255
	lsr r30
	rol r16
	eor r6,r16
	movw r16,r6
	mov r1,r8
	mov r0,r9
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	eor r2,r16
	eor r3,r17
	eor r4,r1
	eor r5,r0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	and r16,r6
	and r17,r7
	and r1,r8
	and r0,r9
	eor r2,r16
	eor r3,r17
	eor r4,r1
	eor r5,r0
	com r3
	com r4
	com r5
	ldi r16,255
	lsr r30
	rol r16
	eor r2,r16
	pop r30
#if defined(RAMPZ)
	elpm r16,Z
#elif defined(__AVR_HAVE_LPMX__)
	lpm r16,Z
#elif defined(__AVR_TINY__)
	ld r16,Z
#else
	lpm
	mov r16,r0
#endif
	inc r30
	push r30
	mov r30,r16
	movw r16,r10
	mov r1,r12
	mov r0,r13
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	eor r14,r16
	eor r15,r17
	eor r24,r1
	eor r25,r0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	and r16,r10
	and r17,r11
	and r1,r12
	and r0,r13
	eor r14,r16
	eor r15,r17
	eor r24,r1
	eor r25,r0
	com r15
	com r24
	com r25
	ldi r16,255
	lsr r30
	rol r16
	eor r14,r16
	movw r16,r14
	mov r1,r24
	mov r0,r25
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	eor r10,r16
	eor r11,r17
	eor r12,r1
	eor r13,r0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	and r16,r14
	and r17,r15
	and r1,r24
	and r0,r25
	eor r10,r16
	eor r11,r17
	eor r12,r1
	eor r13,r0
	com r11
	com r12
	com r13
	ldi r16,255
	lsr r30
	rol r16
	eor r10,r16
	movw r16,r10
	mov r1,r12
	mov r0,r13
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	eor r14,r16
	eor r15,r17
	eor r24,r1
	eor r25,r0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	and r16,r10
	and r17,r11
	and r1,r12
	and r0,r13
	eor r14,r16
	eor r15,r17
	eor r24,r1
	eor r25,r0
	com r15
	com r24
	com r25
	ldi r16,255
	lsr r30
	rol r16
	eor r14,r16
	movw r16,r14
	mov r1,r24
	mov r0,r25
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	eor r10,r16
	eor r11,r17
	eor r12,r1
	eor r13,r0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	and r16,r14
	and r17,r15
	and r1,r24
	and r0,r25
	eor r10,r16
	eor r11,r17
	eor r12,r1
	eor r13,r0
	com r11
	com r12
	com r13
	ldi r16,255
	lsr r30
	rol r16
	eor r10,r16
	movw r16,r10
	mov r1,r12
	mov r0,r13
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	eor r14,r16
	eor r15,r17
	eor r24,r1
	eor r25,r0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	and r16,r10
	and r17,r11
	and r1,r12
	and r0,r13
	eor r14,r16
	eor r15,r17
	eor r24,r1
	eor r25,r0
	com r15
	com r24
	com r25
	ldi r16,255
	lsr r30
	rol r16
	eor r14,r16
	movw r16,r14
	mov r1,r24
	mov r0,r25
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	eor r10,r16
	eor r11,r17
	eor r12,r1
	eor r13,r0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	and r16,r14
	and r17,r15
	and r1,r24
	and r0,r25
	eor r10,r16
	eor r11,r17
	eor r12,r1
	eor r13,r0
	com r11
	com r12
	com r13
	ldi r16,255
	lsr r30
	rol r16
	eor r10,r16
	movw r16,r10
	mov r1,r12
	mov r0,r13
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	eor r14,r16
	eor r15,r17
	eor r24,r1
	eor r25,r0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	and r16,r10
	and r17,r11
	and r1,r12
	and r0,r13
	eor r14,r16
	eor r15,r17
	eor r24,r1
	eor r25,r0
	com r15
	com r24
	com r25
	ldi r16,255
	lsr r30
	rol r16
	eor r14,r16
	movw r16,r14
	mov r1,r24
	mov r0,r25
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	eor r10,r16
	eor r11,r17
	eor r12,r1
	eor r13,r0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	bst r0,7
	lsl r16
	rol r17
	rol r1
	rol r0
	bld r16,0
	and r16,r14
	and r17,r15
	and r1,r24
	and r0,r25
	eor r10,r16
	eor r11,r17
	eor r12,r1
	eor r13,r0
	com r11
	com r12
	com r13
	ldi r16,255
	lsr r30
	rol r16
	eor r10,r16
	pop r30
	ldd r16,Y+1
	ldd r17,Y+2
	ldd r1,Y+3
	ldd r0,Y+4
	eor r16,r2
	eor r17,r3
	eor r1,r4
	eor r0,r5
	com r16
	com r17
	com r1
	com r0
	std Y+1,r16
	std Y+2,r17
	std Y+3,r1
	std Y+4,r0
	ldd r16,Y+5
	ldd r17,Y+6
	ldd r1,Y+7
	ldd r0,Y+8
	eor r16,r6
	eor r17,r7
	eor r1,r8
	eor r0,r9
	com r17
	com r1
	com r0
	std Y+6,r17
	std Y+7,r1
	std Y+8,r0
#if defined(RAMPZ)
	elpm r0,Z
#elif defined(__AVR_HAVE_LPMX__)
	lpm r0,Z
#elif defined(__AVR_TINY__)
	ld r0,Z
#else
	lpm
#endif
	inc r30
	eor r16,r0
	std Y+5,r16
	ldd r16,Y+9
	ldd r17,Y+10
	ldd r1,Y+11
	ldd r0,Y+12
	eor r16,r10
	eor r17,r11
	eor r1,r12
	eor r0,r13
	com r16
	com r17
	com r1
	com r0
	std Y+9,r16
	std Y+10,r17
	std Y+11,r1
	std Y+12,r0
	ldd r16,Y+13
	ldd r17,Y+14
	ldd r1,Y+15
	ldd r0,Y+16
	eor r16,r14
	eor r17,r15
	eor r1,r24
	eor r0,r25
	com r17
	com r1
	com r0
	std Y+14,r17
	std Y+15,r1
	std Y+16,r0
#if defined(RAMPZ)
	elpm r0,Z
#elif defined(__AVR_HAVE_LPMX__)
	lpm r0,Z
#elif defined(__AVR_TINY__)
	ld r0,Z
#else
	lpm
#endif
	inc r30
	eor r16,r0
	std Y+13,r16
	eor r10,r18
	eor r11,r19
	eor r12,r20
	eor r13,r21
	com r10
	com r11
	com r12
	com r13
	eor r14,r22
	eor r15,r23
	eor r24,r26
	eor r25,r27
	com r15
	com r24
	com r25
#if defined(RAMPZ)
	elpm r0,Z
#elif defined(__AVR_HAVE_LPMX__)
	lpm r0,Z
#elif defined(__AVR_TINY__)
	ld r0,Z
#else
	lpm
#endif
	inc r30
	eor r14,r0
	movw r16,r10
	mov r1,r12
	mov r0,r13
	ldd r10,Y+1
	ldd r11,Y+2
	ldd r12,Y+3
	ldd r13,Y+4
	std Y+1,r2
	std Y+2,r3
	std Y+3,r4
	std Y+4,r5
	movw r2,r18
	movw r4,r20
	ldd r18,Y+9
	ldd r19,Y+10
	ldd r20,Y+11
	ldd r21,Y+12
	std Y+9,r16
	std Y+10,r17
	std Y+11,r1
	std Y+12,r0
	movw r16,r14
	mov r1,r24
	mov r0,r25
	ldd r14,Y+5
	ldd r15,Y+6
	ldd r24,Y+7
	ldd r25,Y+8
	std Y+5,r6
	std Y+6,r7
	std Y+7,r8
	std Y+8,r9
	movw r6,r22
	movw r8,r26
	ldd r22,Y+13
	ldd r23,Y+14
	ldd r26,Y+15
	ldd r27,Y+16
	std Y+13,r16
	std Y+14,r17
	std Y+15,r1
	std Y+16,r0
	ldi r17,96
	cpse r30,r17
	rjmp 60b
#if defined(RAMPZ)
	pop r0
	out _SFR_IO_ADDR(RAMPZ),r0
#endif
	pop r30
	pop r31
	st Z,r21
	std Z+1,r20
	std Z+2,r19
	std Z+3,r18
	std Z+16,r27
	std Z+17,r26
	std Z+18,r23
	std Z+19,r22
	std Z+4,r5
	std Z+5,r4
	std Z+6,r3
	std Z+7,r2
	std Z+20,r9
	std Z+21,r8
	std Z+22,r7
	std Z+23,r6
	std Z+32,r13
	std Z+33,r12
	std Z+34,r11
	std Z+35,r10
	std Z+36,r25
	std Z+37,r24
	std Z+38,r15
	std Z+39,r14
	ldd r18,Y+1
	ldd r19,Y+2
	ldd r20,Y+3
	ldd r21,Y+4
	ldd r22,Y+5
	ldd r23,Y+6
	ldd r26,Y+7
	ldd r27,Y+8
	ldd r2,Y+9
	ldd r3,Y+10
	ldd r4,Y+11
	ldd r5,Y+12
	ldd r6,Y+13
	ldd r7,Y+14
	ldd r8,Y+15
	ldd r9,Y+16
	std Z+8,r21
	std Z+9,r20
	std Z+10,r19
	std Z+11,r18
	std Z+12,r27
	std Z+13,r26
	std Z+14,r23
	std Z+15,r22
	std Z+24,r5
	std Z+25,r4
	std Z+26,r3
	std Z+27,r2
	std Z+28,r9
	std Z+29,r8
	std Z+30,r7
	std Z+31,r6
	adiw r28,16
	in r0,0x3f
	cli
	out 0x3e,r29
	out 0x3f,r0
	out 0x3d,r28
	pop r17
	pop r16
	pop r15
	pop r14
	pop r13
	pop r12
	pop r11
	pop r10
	pop r9
	pop r8
	pop r7
	pop r6
	pop r5
	pop r4
	pop r3
	pop r2
	pop r29
	pop r28
	eor r1,r1
	ret
	.size sliscp_light320_permute, .-sliscp_light320_permute

	.text
.global sliscp_light320_swap
	.type sliscp_light320_swap, @function
sliscp_light320_swap:
	movw r30,r24
.L__stack_usage = 2
	ldd r18,Z+4
	ldd r19,Z+5
	ldd r20,Z+6
	ldd r21,Z+7
	ldd r22,Z+16
	ldd r23,Z+17
	ldd r26,Z+18
	ldd r27,Z+19
	std Z+16,r18
	std Z+17,r19
	std Z+18,r20
	std Z+19,r21
	std Z+4,r22
	std Z+5,r23
	std Z+6,r26
	std Z+7,r27
	ret
	.size sliscp_light320_swap, .-sliscp_light320_swap

#endif