#if defined(__AVR__) #include /* Automatically generated - do not edit */ .section .progmem.data,"a",@progbits .p2align 8 .type table_0, @object .size table_0, 72 table_0: .byte 15 .byte 71 .byte 8 .byte 100 .byte 4 .byte 178 .byte 134 .byte 107 .byte 67 .byte 181 .byte 226 .byte 111 .byte 241 .byte 55 .byte 137 .byte 44 .byte 68 .byte 150 .byte 230 .byte 221 .byte 115 .byte 238 .byte 202 .byte 153 .byte 229 .byte 76 .byte 23 .byte 234 .byte 11 .byte 245 .byte 142 .byte 15 .byte 71 .byte 7 .byte 100 .byte 4 .byte 178 .byte 130 .byte 107 .byte 67 .byte 181 .byte 161 .byte 111 .byte 241 .byte 55 .byte 120 .byte 44 .byte 68 .byte 150 .byte 162 .byte 221 .byte 115 .byte 238 .byte 185 .byte 153 .byte 229 .byte 76 .byte 242 .byte 234 .byte 11 .byte 245 .byte 133 .byte 15 .byte 71 .byte 7 .byte 35 .byte 4 .byte 178 .byte 130 .byte 217 .byte 67 .byte 181 .text .global sliscp_light256_permute_spoc .type sliscp_light256_permute_spoc, @function sliscp_light256_permute_spoc: push r28 push r29 push r2 push r3 push r4 push r5 push r6 push r7 push r8 push r9 push r10 push r12 push r13 push r14 push r15 movw r30,r24 in r28,0x3d in r29,0x3e sbiw r28,16 in r0,0x3f cli out 0x3e,r29 out 0x3f,r0 out 0x3d,r28 .L__stack_usage = 31 ld r21,Z ldd r20,Z+1 ldd r19,Z+2 ldd r18,Z+3 ldd r27,Z+4 ldd r26,Z+5 ldd r23,Z+6 ldd r22,Z+7 ldd r5,Z+8 ldd r4,Z+9 ldd r3,Z+10 ldd r2,Z+11 ldd r9,Z+12 ldd r8,Z+13 ldd r7,Z+14 ldd r6,Z+15 std Y+1,r18 std Y+2,r19 std Y+3,r20 std Y+4,r21 std Y+5,r22 std Y+6,r23 std Y+7,r26 std Y+8,r27 std Y+9,r2 std Y+10,r3 std Y+11,r4 std Y+12,r5 std Y+13,r6 std Y+14,r7 std Y+15,r8 std Y+16,r9 ldd r21,Z+16 ldd r20,Z+17 ldd r19,Z+18 ldd r18,Z+19 ldd r27,Z+20 ldd r26,Z+21 ldd r23,Z+22 ldd r22,Z+23 ldd r5,Z+24 ldd r4,Z+25 ldd r3,Z+26 ldd r2,Z+27 ldd r9,Z+28 ldd r8,Z+29 ldd r7,Z+30 ldd r6,Z+31 push r31 push r30 ldi r30,lo8(table_0) ldi r31,hi8(table_0) #if defined(RAMPZ) ldi r24,hh8(table_0) in r0,_SFR_IO_ADDR(RAMPZ) push r0 out _SFR_IO_ADDR(RAMPZ),r24 #endif mov r30,r1 52: #if defined(RAMPZ) elpm r10,Z #elif defined(__AVR_HAVE_LPMX__) lpm r10,Z #elif defined(__AVR_TINY__) ld r10,Z #else lpm mov r10,r0 #endif inc r30 movw r12,r18 movw r14,r20 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 eor r22,r12 eor r23,r13 eor r26,r14 eor r27,r15 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 and r12,r18 and r13,r19 and r14,r20 and r15,r21 eor r22,r12 eor r23,r13 eor r26,r14 eor r27,r15 com r23 com r26 com r27 ldi r24,255 lsr r10 rol r24 eor r22,r24 movw r12,r22 movw r14,r26 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 eor r18,r12 eor r19,r13 eor r20,r14 eor r21,r15 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 and r12,r22 and r13,r23 and r14,r26 and r15,r27 eor r18,r12 eor r19,r13 eor r20,r14 eor r21,r15 com r19 com r20 com r21 ldi r24,255 lsr r10 rol r24 eor r18,r24 movw r12,r18 movw r14,r20 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 eor r22,r12 eor r23,r13 eor r26,r14 eor r27,r15 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 and r12,r18 and r13,r19 and r14,r20 and r15,r21 eor r22,r12 eor r23,r13 eor r26,r14 eor r27,r15 com r23 com r26 com r27 ldi r24,255 lsr r10 rol r24 eor r22,r24 movw r12,r22 movw r14,r26 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 eor r18,r12 eor r19,r13 eor r20,r14 eor r21,r15 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 and r12,r22 and r13,r23 and r14,r26 and r15,r27 eor r18,r12 eor r19,r13 eor r20,r14 eor r21,r15 com r19 com r20 com r21 ldi r24,255 lsr r10 rol r24 eor r18,r24 movw r12,r18 movw r14,r20 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 eor r22,r12 eor r23,r13 eor r26,r14 eor r27,r15 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 and r12,r18 and r13,r19 and r14,r20 and r15,r21 eor r22,r12 eor r23,r13 eor r26,r14 eor r27,r15 com r23 com r26 com r27 ldi r24,255 lsr r10 rol r24 eor r22,r24 movw r12,r22 movw r14,r26 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 eor r18,r12 eor r19,r13 eor r20,r14 eor r21,r15 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 and r12,r22 and r13,r23 and r14,r26 and r15,r27 eor r18,r12 eor r19,r13 eor r20,r14 eor r21,r15 com r19 com r20 com r21 ldi r24,255 lsr r10 rol r24 eor r18,r24 movw r12,r18 movw r14,r20 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 eor r22,r12 eor r23,r13 eor r26,r14 eor r27,r15 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 and r12,r18 and r13,r19 and r14,r20 and r15,r21 eor r22,r12 eor r23,r13 eor r26,r14 eor r27,r15 com r23 com r26 com r27 ldi r24,255 lsr r10 rol r24 eor r22,r24 movw r12,r22 movw r14,r26 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 eor r18,r12 eor r19,r13 eor r20,r14 eor r21,r15 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 and r12,r22 and r13,r23 and r14,r26 and r15,r27 eor r18,r12 eor r19,r13 eor r20,r14 eor r21,r15 com r19 com r20 com r21 ldi r24,255 lsr r10 rol r24 eor r18,r24 #if defined(RAMPZ) elpm r10,Z #elif defined(__AVR_HAVE_LPMX__) lpm r10,Z #elif defined(__AVR_TINY__) ld r10,Z #else lpm mov r10,r0 #endif inc r30 movw r12,r2 movw r14,r4 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 eor r6,r12 eor r7,r13 eor r8,r14 eor r9,r15 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 and r12,r2 and r13,r3 and r14,r4 and r15,r5 eor r6,r12 eor r7,r13 eor r8,r14 eor r9,r15 com r7 com r8 com r9 ldi r24,255 lsr r10 rol r24 eor r6,r24 movw r12,r6 movw r14,r8 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 eor r2,r12 eor r3,r13 eor r4,r14 eor r5,r15 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 and r12,r6 and r13,r7 and r14,r8 and r15,r9 eor r2,r12 eor r3,r13 eor r4,r14 eor r5,r15 com r3 com r4 com r5 ldi r24,255 lsr r10 rol r24 eor r2,r24 movw r12,r2 movw r14,r4 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 eor r6,r12 eor r7,r13 eor r8,r14 eor r9,r15 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 and r12,r2 and r13,r3 and r14,r4 and r15,r5 eor r6,r12 eor r7,r13 eor r8,r14 eor r9,r15 com r7 com r8 com r9 ldi r24,255 lsr r10 rol r24 eor r6,r24 movw r12,r6 movw r14,r8 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 eor r2,r12 eor r3,r13 eor r4,r14 eor r5,r15 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 and r12,r6 and r13,r7 and r14,r8 and r15,r9 eor r2,r12 eor r3,r13 eor r4,r14 eor r5,r15 com r3 com r4 com r5 ldi r24,255 lsr r10 rol r24 eor r2,r24 movw r12,r2 movw r14,r4 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 eor r6,r12 eor r7,r13 eor r8,r14 eor r9,r15 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 and r12,r2 and r13,r3 and r14,r4 and r15,r5 eor r6,r12 eor r7,r13 eor r8,r14 eor r9,r15 com r7 com r8 com r9 ldi r24,255 lsr r10 rol r24 eor r6,r24 movw r12,r6 movw r14,r8 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 eor r2,r12 eor r3,r13 eor r4,r14 eor r5,r15 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 and r12,r6 and r13,r7 and r14,r8 and r15,r9 eor r2,r12 eor r3,r13 eor r4,r14 eor r5,r15 com r3 com r4 com r5 ldi r24,255 lsr r10 rol r24 eor r2,r24 movw r12,r2 movw r14,r4 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 eor r6,r12 eor r7,r13 eor r8,r14 eor r9,r15 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 and r12,r2 and r13,r3 and r14,r4 and r15,r5 eor r6,r12 eor r7,r13 eor r8,r14 eor r9,r15 com r7 com r8 com r9 ldi r24,255 lsr r10 rol r24 eor r6,r24 movw r12,r6 movw r14,r8 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 eor r2,r12 eor r3,r13 eor r4,r14 eor r5,r15 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 lsl r12 rol r13 rol r14 rol r15 adc r12,r1 and r12,r6 and r13,r7 and r14,r8 and r15,r9 eor r2,r12 eor r3,r13 eor r4,r14 eor r5,r15 com r3 com r4 com r5 ldi r24,255 lsr r10 rol r24 eor r2,r24 ldd r12,Y+1 ldd r13,Y+2 ldd r14,Y+3 ldd r15,Y+4 com r12 com r13 com r14 com r15 eor r12,r18 eor r13,r19 eor r14,r20 eor r15,r21 std Y+1,r18 std Y+2,r19 std Y+3,r20 std Y+4,r21 ldd r18,Y+9 ldd r19,Y+10 ldd r20,Y+11 ldd r21,Y+12 com r18 com r19 com r20 com r21 eor r18,r2 eor r19,r3 eor r20,r4 eor r21,r5 std Y+9,r2 std Y+10,r3 std Y+11,r4 std Y+12,r5 movw r2,r12 movw r4,r14 ldd r12,Y+5 ldd r13,Y+6 ldd r14,Y+7 ldd r15,Y+8 com r13 com r14 com r15 #if defined(RAMPZ) elpm r10,Z #elif defined(__AVR_HAVE_LPMX__) lpm r10,Z #elif defined(__AVR_TINY__) ld r10,Z #else lpm mov r10,r0 #endif eor r12,r10 inc r30 eor r12,r22 eor r13,r23 eor r14,r26 eor r15,r27 std Y+5,r22 std Y+6,r23 std Y+7,r26 std Y+8,r27 ldd r22,Y+13 ldd r23,Y+14 ldd r26,Y+15 ldd r27,Y+16 com r23 com r26 com r27 #if defined(RAMPZ) elpm r10,Z #elif defined(__AVR_HAVE_LPMX__) lpm r10,Z #elif defined(__AVR_TINY__) ld r10,Z #else lpm mov r10,r0 #endif eor r22,r10 inc r30 eor r22,r6 eor r23,r7 eor r26,r8 eor r27,r9 std Y+13,r6 std Y+14,r7 std Y+15,r8 std Y+16,r9 movw r6,r12 movw r8,r14 ldi r25,72 cpse r30,r25 rjmp 52b #if defined(RAMPZ) pop r0 out _SFR_IO_ADDR(RAMPZ),r0 #endif pop r30 pop r31 std Z+16,r21 std Z+17,r20 std Z+18,r19 std Z+19,r18 std Z+20,r27 std Z+21,r26 std Z+22,r23 std Z+23,r22 std Z+24,r5 std Z+25,r4 std Z+26,r3 std Z+27,r2 std Z+28,r9 std Z+29,r8 std Z+30,r7 std Z+31,r6 ldd r18,Y+1 ldd r19,Y+2 ldd r20,Y+3 ldd r21,Y+4 ldd r22,Y+5 ldd r23,Y+6 ldd r26,Y+7 ldd r27,Y+8 ldd r2,Y+9 ldd r3,Y+10 ldd r4,Y+11 ldd r5,Y+12 ldd r6,Y+13 ldd r7,Y+14 ldd r8,Y+15 ldd r9,Y+16 st Z,r21 std Z+1,r20 std Z+2,r19 std Z+3,r18 std Z+4,r27 std Z+5,r26 std Z+6,r23 std Z+7,r22 std Z+8,r5 std Z+9,r4 std Z+10,r3 std Z+11,r2 std Z+12,r9 std Z+13,r8 std Z+14,r7 std Z+15,r6 adiw r28,16 in r0,0x3f cli out 0x3e,r29 out 0x3f,r0 out 0x3d,r28 pop r15 pop r14 pop r13 pop r12 pop r10 pop r9 pop r8 pop r7 pop r6 pop r5 pop r4 pop r3 pop r2 pop r29 pop r28 ret .size sliscp_light256_permute_spoc, .-sliscp_light256_permute_spoc .text .global sliscp_light256_swap_spoc .type sliscp_light256_swap_spoc, @function sliscp_light256_swap_spoc: movw r30,r24 .L__stack_usage = 2 ldd r18,Z+8 ldd r19,Z+9 ldd r20,Z+10 ldd r21,Z+11 ldd r22,Z+16 ldd r23,Z+17 ldd r26,Z+18 ldd r27,Z+19 std Z+16,r18 std Z+17,r19 std Z+18,r20 std Z+19,r21 std Z+8,r22 std Z+9,r23 std Z+10,r26 std Z+11,r27 ldd r18,Z+12 ldd r19,Z+13 ldd r20,Z+14 ldd r21,Z+15 ldd r22,Z+20 ldd r23,Z+21 ldd r26,Z+22 ldd r27,Z+23 std Z+20,r18 std Z+21,r19 std Z+22,r20 std Z+23,r21 std Z+12,r22 std Z+13,r23 std Z+14,r26 std Z+15,r27 ret .size sliscp_light256_swap_spoc, .-sliscp_light256_swap_spoc #endif