#if defined(__AVR__) #include /* Automatically generated - do not edit */ .section .progmem.data,"a",@progbits .p2align 8 .type table_0, @object .size table_0, 72 table_0: .byte 7 .byte 39 .byte 8 .byte 41 .byte 4 .byte 52 .byte 12 .byte 29 .byte 6 .byte 46 .byte 10 .byte 51 .byte 37 .byte 25 .byte 47 .byte 42 .byte 23 .byte 53 .byte 56 .byte 31 .byte 28 .byte 15 .byte 36 .byte 16 .byte 18 .byte 8 .byte 54 .byte 24 .byte 59 .byte 12 .byte 13 .byte 20 .byte 38 .byte 10 .byte 43 .byte 30 .byte 21 .byte 47 .byte 62 .byte 49 .byte 63 .byte 56 .byte 1 .byte 9 .byte 32 .byte 36 .byte 33 .byte 45 .byte 48 .byte 54 .byte 17 .byte 27 .byte 40 .byte 13 .byte 57 .byte 22 .byte 60 .byte 43 .byte 5 .byte 61 .byte 34 .byte 62 .byte 39 .byte 3 .byte 19 .byte 1 .byte 52 .byte 2 .byte 26 .byte 33 .byte 46 .byte 35 .text .global sliscp_light192_permute .type sliscp_light192_permute, @function sliscp_light192_permute: push r28 push r29 push r2 push r3 push r4 push r5 push r6 push r7 push r8 push r9 push r10 push r11 push r12 push r13 push r14 push r15 push r16 push r17 movw r30,r24 .L__stack_usage = 18 ld r20,Z ldd r19,Z+1 ldd r18,Z+2 ldd r21,Z+3 ldd r23,Z+4 ldd r22,Z+5 ldd r28,Z+6 ldd r27,Z+7 ldd r26,Z+8 ldd r29,Z+9 ldd r3,Z+10 ldd r2,Z+11 ldd r6,Z+12 ldd r5,Z+13 ldd r4,Z+14 ldd r7,Z+15 ldd r9,Z+16 ldd r8,Z+17 ldd r12,Z+18 ldd r11,Z+19 ldd r10,Z+20 ldd r13,Z+21 ldd r15,Z+22 ldd r14,Z+23 push r31 push r30 ldi r30,lo8(table_0) ldi r31,hi8(table_0) #if defined(RAMPZ) ldi r24,hh8(table_0) in r0,_SFR_IO_ADDR(RAMPZ) push r0 out _SFR_IO_ADDR(RAMPZ),r24 #endif ldi r24,0 28: mov r30,r24 #if defined(RAMPZ) elpm r25,Z #elif defined(__AVR_HAVE_LPMX__) lpm r25,Z #elif defined(__AVR_TINY__) ld r25,Z #else lpm mov r25,r0 #endif inc r24 movw r16,r26 mov r1,r28 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 eor r2,r16 eor r3,r17 eor r29,r1 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 and r16,r26 and r17,r27 and r1,r28 eor r2,r16 eor r3,r17 eor r29,r1 com r3 com r29 ldi r16,255 lsr r25 rol r16 eor r2,r16 movw r16,r2 mov r1,r29 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 eor r26,r16 eor r27,r17 eor r28,r1 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 and r16,r2 and r17,r3 and r1,r29 eor r26,r16 eor r27,r17 eor r28,r1 com r27 com r28 ldi r16,255 lsr r25 rol r16 eor r26,r16 movw r16,r26 mov r1,r28 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 eor r2,r16 eor r3,r17 eor r29,r1 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 and r16,r26 and r17,r27 and r1,r28 eor r2,r16 eor r3,r17 eor r29,r1 com r3 com r29 ldi r16,255 lsr r25 rol r16 eor r2,r16 movw r16,r2 mov r1,r29 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 eor r26,r16 eor r27,r17 eor r28,r1 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 and r16,r2 and r17,r3 and r1,r29 eor r26,r16 eor r27,r17 eor r28,r1 com r27 com r28 ldi r16,255 lsr r25 rol r16 eor r26,r16 movw r16,r26 mov r1,r28 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 eor r2,r16 eor r3,r17 eor r29,r1 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 and r16,r26 and r17,r27 and r1,r28 eor r2,r16 eor r3,r17 eor r29,r1 com r3 com r29 ldi r16,255 lsr r25 rol r16 eor r2,r16 movw r16,r2 mov r1,r29 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 eor r26,r16 eor r27,r17 eor r28,r1 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 and r16,r2 and r17,r3 and r1,r29 eor r26,r16 eor r27,r17 eor r28,r1 com r27 com r28 ldi r16,255 lsr r25 rol r16 eor r26,r16 mov r30,r24 #if defined(RAMPZ) elpm r25,Z #elif defined(__AVR_HAVE_LPMX__) lpm r25,Z #elif defined(__AVR_TINY__) ld r25,Z #else lpm mov r25,r0 #endif inc r24 movw r16,r10 mov r1,r12 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 eor r14,r16 eor r15,r17 eor r13,r1 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 and r16,r10 and r17,r11 and r1,r12 eor r14,r16 eor r15,r17 eor r13,r1 com r15 com r13 ldi r16,255 lsr r25 rol r16 eor r14,r16 movw r16,r14 mov r1,r13 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 eor r10,r16 eor r11,r17 eor r12,r1 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 and r16,r14 and r17,r15 and r1,r13 eor r10,r16 eor r11,r17 eor r12,r1 com r11 com r12 ldi r16,255 lsr r25 rol r16 eor r10,r16 movw r16,r10 mov r1,r12 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 eor r14,r16 eor r15,r17 eor r13,r1 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 and r16,r10 and r17,r11 and r1,r12 eor r14,r16 eor r15,r17 eor r13,r1 com r15 com r13 ldi r16,255 lsr r25 rol r16 eor r14,r16 movw r16,r14 mov r1,r13 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 eor r10,r16 eor r11,r17 eor r12,r1 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 and r16,r14 and r17,r15 and r1,r13 eor r10,r16 eor r11,r17 eor r12,r1 com r11 com r12 ldi r16,255 lsr r25 rol r16 eor r10,r16 movw r16,r10 mov r1,r12 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 eor r14,r16 eor r15,r17 eor r13,r1 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 and r16,r10 and r17,r11 and r1,r12 eor r14,r16 eor r15,r17 eor r13,r1 com r15 com r13 ldi r16,255 lsr r25 rol r16 eor r14,r16 movw r16,r14 mov r1,r13 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 eor r10,r16 eor r11,r17 eor r12,r1 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 bst r1,7 lsl r16 rol r17 rol r1 bld r16,0 and r16,r14 and r17,r15 and r1,r13 eor r10,r16 eor r11,r17 eor r12,r1 com r11 com r12 ldi r16,255 lsr r25 rol r16 eor r10,r16 com r18 com r19 com r20 com r23 com r21 mov r30,r24 #if defined(RAMPZ) elpm r25,Z #elif defined(__AVR_HAVE_LPMX__) lpm r25,Z #elif defined(__AVR_TINY__) ld r25,Z #else lpm mov r25,r0 #endif eor r22,r25 inc r24 com r4 com r5 com r6 com r9 com r7 mov r30,r24 #if defined(RAMPZ) elpm r25,Z #elif defined(__AVR_HAVE_LPMX__) lpm r25,Z #elif defined(__AVR_TINY__) ld r25,Z #else lpm mov r25,r0 #endif eor r8,r25 inc r24 movw r16,r18 mov r1,r20 eor r16,r26 eor r17,r27 eor r1,r28 movw r18,r26 mov r20,r28 movw r26,r4 mov r28,r6 eor r26,r10 eor r27,r11 eor r28,r12 movw r4,r10 mov r6,r12 movw r10,r16 mov r12,r1 movw r16,r22 mov r1,r21 eor r16,r2 eor r17,r3 eor r1,r29 movw r22,r2 mov r21,r29 movw r2,r8 mov r29,r7 eor r2,r14 eor r3,r15 eor r29,r13 movw r8,r14 mov r7,r13 movw r14,r16 mov r13,r1 ldi r17,72 cpse r24,r17 rjmp 28b #if defined(RAMPZ) pop r0 out _SFR_IO_ADDR(RAMPZ),r0 #endif pop r30 pop r31 st Z,r20 std Z+1,r19 std Z+2,r18 std Z+3,r21 std Z+4,r23 std Z+5,r22 std Z+6,r28 std Z+7,r27 std Z+8,r26 std Z+9,r29 std Z+10,r3 std Z+11,r2 std Z+12,r6 std Z+13,r5 std Z+14,r4 std Z+15,r7 std Z+16,r9 std Z+17,r8 std Z+18,r12 std Z+19,r11 std Z+20,r10 std Z+21,r13 std Z+22,r15 std Z+23,r14 pop r17 pop r16 pop r15 pop r14 pop r13 pop r12 pop r11 pop r10 pop r9 pop r8 pop r7 pop r6 pop r5 pop r4 pop r3 pop r2 pop r29 pop r28 eor r1,r1 ret .size sliscp_light192_permute, .-sliscp_light192_permute #endif