#if defined(__AVR__) #include /* Automatically generated - do not edit */ #include "internal-gift128-config.h" #if GIFT128_VARIANT == GIFT128_VARIANT_FULL .section .progmem.data,"a",@progbits .p2align 8 .type table_0, @object .size table_0, 160 table_0: .byte 8 .byte 0 .byte 0 .byte 16 .byte 0 .byte 128 .byte 1 .byte 128 .byte 2 .byte 0 .byte 0 .byte 84 .byte 129 .byte 1 .byte 1 .byte 1 .byte 31 .byte 0 .byte 0 .byte 128 .byte 128 .byte 136 .byte 136 .byte 16 .byte 0 .byte 224 .byte 1 .byte 96 .byte 2 .byte 0 .byte 80 .byte 81 .byte 128 .byte 1 .byte 3 .byte 3 .byte 47 .byte 0 .byte 0 .byte 128 .byte 128 .byte 136 .byte 8 .byte 16 .byte 0 .byte 96 .byte 1 .byte 96 .byte 2 .byte 0 .byte 80 .byte 65 .byte 128 .byte 0 .byte 3 .byte 3 .byte 39 .byte 0 .byte 0 .byte 128 .byte 128 .byte 136 .byte 0 .byte 16 .byte 0 .byte 224 .byte 1 .byte 64 .byte 2 .byte 0 .byte 80 .byte 17 .byte 128 .byte 1 .byte 2 .byte 3 .byte 43 .byte 0 .byte 0 .byte 128 .byte 128 .byte 8 .byte 8 .byte 16 .byte 0 .byte 64 .byte 1 .byte 96 .byte 2 .byte 0 .byte 64 .byte 1 .byte 128 .byte 0 .byte 2 .byte 2 .byte 33 .byte 0 .byte 0 .byte 128 .byte 128 .byte 0 .byte 0 .byte 16 .byte 0 .byte 192 .byte 1 .byte 0 .byte 2 .byte 0 .byte 0 .byte 81 .byte 128 .byte 1 .byte 1 .byte 3 .byte 46 .byte 0 .byte 0 .byte 128 .byte 0 .byte 136 .byte 8 .byte 16 .byte 0 .byte 32 .byte 1 .byte 96 .byte 2 .byte 0 .byte 80 .byte 64 .byte 128 .byte 0 .byte 3 .byte 1 .byte 6 .byte 0 .byte 0 .byte 128 .byte 8 .byte 136 .byte 0 .byte 16 .byte 0 .byte 160 .byte 1 .byte 192 .byte 2 .byte 0 .byte 80 .byte 20 .byte 129 .byte 1 .byte 2 .byte 1 .byte 26 .byte 0 .byte 0 .byte 128 .text .global gift128b_init .type gift128b_init, @function gift128b_init: push r28 push r29 push r2 push r3 push r4 push r5 push r6 push r7 push r8 push r9 push r10 push r11 push r12 push r13 push r14 push r15 push r16 push r17 movw r30,r24 movw r26,r22 .L__stack_usage = 18 ld r13,X+ ld r12,X+ ld r11,X+ ld r10,X+ ld r5,X+ ld r4,X+ ld r3,X+ ld r2,X+ ld r9,X+ ld r8,X+ ld r7,X+ ld r6,X+ ld r29,X+ ld r28,X+ ld r23,X+ ld r22,X+ st Z+,r22 st Z+,r23 st Z+,r28 st Z+,r29 st Z+,r2 st Z+,r3 st Z+,r4 st Z+,r5 st Z+,r6 st Z+,r7 st Z+,r8 st Z+,r9 st Z+,r10 st Z+,r11 st Z+,r12 st Z+,r13 ldi r24,4 33: st Z+,r2 st Z+,r3 st Z+,r4 st Z+,r5 lsl r22 rol r23 adc r22,r1 lsl r22 rol r23 adc r22,r1 lsl r22 rol r23 adc r22,r1 lsl r22 rol r23 adc r22,r1 mov r0,r1 lsr r29 ror r28 ror r0 lsr r29 ror r28 ror r0 or r29,r0 st Z+,r22 st Z+,r23 st Z+,r28 st Z+,r29 mov r0,r22 mov r22,r2 mov r2,r0 mov r0,r23 mov r23,r3 mov r3,r0 mov r0,r28 mov r28,r4 mov r4,r0 mov r0,r29 mov r29,r5 mov r5,r0 st Z+,r10 st Z+,r11 st Z+,r12 st Z+,r13 lsl r6 rol r7 adc r6,r1 lsl r6 rol r7 adc r6,r1 lsl r6 rol r7 adc r6,r1 lsl r6 rol r7 adc r6,r1 mov r0,r1 lsr r9 ror r8 ror r0 lsr r9 ror r8 ror r0 or r9,r0 st Z+,r6 st Z+,r7 st Z+,r8 st Z+,r9 mov r0,r6 mov r6,r10 mov r10,r0 mov r0,r7 mov r7,r11 mov r11,r0 mov r0,r8 mov r8,r12 mov r12,r0 mov r0,r9 mov r9,r13 mov r13,r0 dec r24 breq 5115f rjmp 33b 5115: subi r30,80 sbc r31,r1 ldi r24,2 119: ld r22,Z ldd r23,Z+1 ldd r28,Z+2 ldd r29,Z+3 movw r18,r22 movw r20,r28 mov r18,r19 mov r19,r20 mov r20,r21 mov r21,r1 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 eor r20,r28 eor r21,r29 andi r18,85 mov r19,r1 andi r20,85 mov r21,r1 eor r22,r18 eor r23,r19 eor r28,r20 eor r29,r21 mov r21,r20 mov r20,r19 mov r19,r18 mov r18,r1 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r28,r20 eor r29,r21 movw r18,r22 movw r20,r28 mov r18,r19 mov r19,r20 mov r20,r21 mov r21,r1 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 eor r20,r28 eor r21,r29 andi r18,15 mov r19,r1 andi r20,15 mov r21,r1 eor r22,r18 eor r23,r19 eor r28,r20 eor r29,r21 mov r21,r20 mov r20,r19 mov r19,r18 mov r18,r1 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r28,r20 eor r29,r21 movw r18,r22 movw r20,r28 movw r18,r20 mov r20,r1 mov r21,r1 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 andi r18,51 andi r19,51 eor r22,r18 eor r23,r19 mov r20,r1 mov r21,r1 movw r20,r18 mov r18,r1 mov r19,r1 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r28,r20 eor r29,r21 st Z,r29 std Z+1,r23 std Z+2,r28 std Z+3,r22 ldd r22,Z+4 ldd r23,Z+5 ldd r28,Z+6 ldd r29,Z+7 movw r18,r22 movw r20,r28 mov r18,r19 mov r19,r20 mov r20,r21 mov r21,r1 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 eor r20,r28 eor r21,r29 andi r18,85 mov r19,r1 andi r20,85 mov r21,r1 eor r22,r18 eor r23,r19 eor r28,r20 eor r29,r21 mov r21,r20 mov r20,r19 mov r19,r18 mov r18,r1 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r28,r20 eor r29,r21 movw r18,r22 movw r20,r28 mov r18,r19 mov r19,r20 mov r20,r21 mov r21,r1 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 eor r20,r28 eor r21,r29 andi r18,15 mov r19,r1 andi r20,15 mov r21,r1 eor r22,r18 eor r23,r19 eor r28,r20 eor r29,r21 mov r21,r20 mov r20,r19 mov r19,r18 mov r18,r1 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r28,r20 eor r29,r21 movw r18,r22 movw r20,r28 movw r18,r20 mov r20,r1 mov r21,r1 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 andi r18,51 andi r19,51 eor r22,r18 eor r23,r19 mov r20,r1 mov r21,r1 movw r20,r18 mov r18,r1 mov r19,r1 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r28,r20 eor r29,r21 std Z+4,r29 std Z+5,r23 std Z+6,r28 std Z+7,r22 ldd r22,Z+8 ldd r23,Z+9 ldd r28,Z+10 ldd r29,Z+11 movw r18,r22 movw r20,r28 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 eor r20,r28 eor r21,r29 andi r18,17 andi r19,17 andi r20,17 andi r21,17 eor r22,r18 eor r23,r19 eor r28,r20 eor r29,r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r28,r20 eor r29,r21 movw r18,r22 movw r20,r28 mov r0,r1 lsl r18 rol r19 rol r20 rol r21 rol r0 lsl r18 rol r19 rol r20 rol r21 rol r0 mov r18,r19 mov r19,r20 mov r20,r21 mov r21,r0 eor r18,r22 eor r19,r23 eor r20,r28 eor r21,r29 andi r18,3 andi r19,3 andi r20,3 andi r21,3 eor r22,r18 eor r23,r19 eor r28,r20 eor r29,r21 mov r0,r1 lsr r21 ror r20 ror r19 ror r18 ror r0 lsr r21 ror r20 ror r19 ror r18 ror r0 mov r21,r20 mov r20,r19 mov r19,r18 mov r18,r0 eor r22,r18 eor r23,r19 eor r28,r20 eor r29,r21 movw r18,r22 movw r20,r28 mov r18,r19 mov r19,r20 mov r20,r21 mov r21,r1 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 eor r20,r28 eor r21,r29 andi r18,15 mov r19,r1 andi r20,15 mov r21,r1 eor r22,r18 eor r23,r19 eor r28,r20 eor r29,r21 mov r21,r20 mov r20,r19 mov r19,r18 mov r18,r1 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r28,r20 eor r29,r21 std Z+8,r29 std Z+9,r23 std Z+10,r28 std Z+11,r22 ldd r22,Z+12 ldd r23,Z+13 ldd r28,Z+14 ldd r29,Z+15 movw r18,r22 movw r20,r28 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 eor r20,r28 eor r21,r29 andi r18,17 andi r19,17 andi r20,17 andi r21,17 eor r22,r18 eor r23,r19 eor r28,r20 eor r29,r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r28,r20 eor r29,r21 movw r18,r22 movw r20,r28 mov r0,r1 lsl r18 rol r19 rol r20 rol r21 rol r0 lsl r18 rol r19 rol r20 rol r21 rol r0 mov r18,r19 mov r19,r20 mov r20,r21 mov r21,r0 eor r18,r22 eor r19,r23 eor r20,r28 eor r21,r29 andi r18,3 andi r19,3 andi r20,3 andi r21,3 eor r22,r18 eor r23,r19 eor r28,r20 eor r29,r21 mov r0,r1 lsr r21 ror r20 ror r19 ror r18 ror r0 lsr r21 ror r20 ror r19 ror r18 ror r0 mov r21,r20 mov r20,r19 mov r19,r18 mov r18,r0 eor r22,r18 eor r23,r19 eor r28,r20 eor r29,r21 movw r18,r22 movw r20,r28 mov r18,r19 mov r19,r20 mov r20,r21 mov r21,r1 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 eor r20,r28 eor r21,r29 andi r18,15 mov r19,r1 andi r20,15 mov r21,r1 eor r22,r18 eor r23,r19 eor r28,r20 eor r29,r21 mov r21,r20 mov r20,r19 mov r19,r18 mov r18,r1 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r28,r20 eor r29,r21 std Z+12,r29 std Z+13,r23 std Z+14,r28 std Z+15,r22 ldd r22,Z+16 ldd r23,Z+17 ldd r28,Z+18 ldd r29,Z+19 movw r18,r22 movw r20,r28 mov r0,r1 lsl r19 rol r20 rol r21 rol r0 movw r18,r20 mov r20,r0 mov r21,r1 eor r18,r22 eor r19,r23 andi r18,170 andi r19,170 eor r22,r18 eor r23,r19 mov r20,r1 mov r21,r1 mov r0,r1 lsr r20 ror r19 ror r18 ror r0 movw r20,r18 mov r19,r0 mov r18,r1 eor r22,r18 eor r23,r19 eor r28,r20 eor r29,r21 movw r18,r22 movw r20,r28 movw r18,r20 mov r20,r1 mov r21,r1 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 andi r18,51 andi r19,51 eor r22,r18 eor r23,r19 mov r20,r1 mov r21,r1 movw r20,r18 mov r18,r1 mov r19,r1 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r28,r20 eor r29,r21 movw r18,r22 movw r20,r28 mov r18,r19 mov r19,r20 mov r20,r21 mov r21,r1 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 andi r18,240 andi r19,240 eor r22,r18 eor r23,r19 mov r20,r1 mov r21,r1 mov r21,r20 mov r20,r19 mov r19,r18 mov r18,r1 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r28,r20 eor r29,r21 std Z+16,r29 std Z+17,r23 std Z+18,r28 std Z+19,r22 ldd r22,Z+20 ldd r23,Z+21 ldd r28,Z+22 ldd r29,Z+23 movw r18,r22 movw r20,r28 mov r0,r1 lsl r19 rol r20 rol r21 rol r0 movw r18,r20 mov r20,r0 mov r21,r1 eor r18,r22 eor r19,r23 andi r18,170 andi r19,170 eor r22,r18 eor r23,r19 mov r20,r1 mov r21,r1 mov r0,r1 lsr r20 ror r19 ror r18 ror r0 movw r20,r18 mov r19,r0 mov r18,r1 eor r22,r18 eor r23,r19 eor r28,r20 eor r29,r21 movw r18,r22 movw r20,r28 movw r18,r20 mov r20,r1 mov r21,r1 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 andi r18,51 andi r19,51 eor r22,r18 eor r23,r19 mov r20,r1 mov r21,r1 movw r20,r18 mov r18,r1 mov r19,r1 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r28,r20 eor r29,r21 movw r18,r22 movw r20,r28 mov r18,r19 mov r19,r20 mov r20,r21 mov r21,r1 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 andi r18,240 andi r19,240 eor r22,r18 eor r23,r19 mov r20,r1 mov r21,r1 mov r21,r20 mov r20,r19 mov r19,r18 mov r18,r1 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r28,r20 eor r29,r21 std Z+20,r29 std Z+21,r23 std Z+22,r28 std Z+23,r22 ldd r22,Z+24 ldd r23,Z+25 ldd r28,Z+26 ldd r29,Z+27 movw r18,r22 movw r20,r28 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 eor r20,r28 eor r21,r29 andi r18,10 andi r19,10 andi r20,10 andi r21,10 eor r22,r18 eor r23,r19 eor r28,r20 eor r29,r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r28,r20 eor r29,r21 movw r18,r22 movw r20,r28 mov r0,r1 lsl r18 rol r19 rol r20 rol r21 rol r0 lsl r18 rol r19 rol r20 rol r21 rol r0 mov r18,r19 mov r19,r20 mov r20,r21 mov r21,r0 eor r18,r22 eor r19,r23 eor r20,r28 eor r21,r29 andi r18,204 mov r19,r1 andi r20,204 mov r21,r1 eor r22,r18 eor r23,r19 eor r28,r20 eor r29,r21 mov r0,r1 lsr r21 ror r20 ror r19 ror r18 ror r0 lsr r21 ror r20 ror r19 ror r18 ror r0 mov r21,r20 mov r20,r19 mov r19,r18 mov r18,r0 eor r22,r18 eor r23,r19 eor r28,r20 eor r29,r21 movw r18,r22 movw r20,r28 mov r18,r19 mov r19,r20 mov r20,r21 mov r21,r1 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 andi r18,240 andi r19,240 eor r22,r18 eor r23,r19 mov r20,r1 mov r21,r1 mov r21,r20 mov r20,r19 mov r19,r18 mov r18,r1 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r28,r20 eor r29,r21 std Z+24,r29 std Z+25,r23 std Z+26,r28 std Z+27,r22 ldd r22,Z+28 ldd r23,Z+29 ldd r28,Z+30 ldd r29,Z+31 movw r18,r22 movw r20,r28 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 eor r20,r28 eor r21,r29 andi r18,10 andi r19,10 andi r20,10 andi r21,10 eor r22,r18 eor r23,r19 eor r28,r20 eor r29,r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r28,r20 eor r29,r21 movw r18,r22 movw r20,r28 mov r0,r1 lsl r18 rol r19 rol r20 rol r21 rol r0 lsl r18 rol r19 rol r20 rol r21 rol r0 mov r18,r19 mov r19,r20 mov r20,r21 mov r21,r0 eor r18,r22 eor r19,r23 eor r20,r28 eor r21,r29 andi r18,204 mov r19,r1 andi r20,204 mov r21,r1 eor r22,r18 eor r23,r19 eor r28,r20 eor r29,r21 mov r0,r1 lsr r21 ror r20 ror r19 ror r18 ror r0 lsr r21 ror r20 ror r19 ror r18 ror r0 mov r21,r20 mov r20,r19 mov r19,r18 mov r18,r0 eor r22,r18 eor r23,r19 eor r28,r20 eor r29,r21 movw r18,r22 movw r20,r28 mov r18,r19 mov r19,r20 mov r20,r21 mov r21,r1 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 eor r18,r22 eor r19,r23 andi r18,240 andi r19,240 eor r22,r18 eor r23,r19 mov r20,r1 mov r21,r1 mov r21,r20 mov r20,r19 mov r19,r18 mov r18,r1 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 eor r22,r18 eor r23,r19 eor r28,r20 eor r29,r21 std Z+28,r29 std Z+29,r23 std Z+30,r28 std Z+31,r22 dec r24 breq 1268f adiw r30,40 rjmp 119b 1268: adiw r30,40 movw r26,r30 subi r26,80 sbc r27,r1 ldi r24,6 1274: ld r22,X+ ld r23,X+ ld r28,X+ ld r29,X+ ld r2,X+ ld r3,X+ ld r4,X+ ld r5,X+ movw r18,r2 movw r20,r4 movw r18,r20 mov r20,r1 mov r21,r1 eor r18,r2 eor r19,r3 andi r18,51 andi r19,51 eor r2,r18 eor r3,r19 mov r20,r1 mov r21,r1 movw r20,r18 mov r18,r1 mov r19,r1 eor r2,r18 eor r3,r19 eor r4,r20 eor r5,r21 movw r18,r2 movw r20,r4 lsr r21 ror r20 ror r19 ror r18 eor r18,r2 eor r19,r3 eor r20,r4 eor r21,r5 andi r18,68 andi r19,68 andi r20,85 andi r21,85 eor r2,r18 eor r3,r19 eor r4,r20 eor r5,r21 lsl r18 rol r19 rol r20 rol r21 eor r2,r18 eor r3,r19 eor r4,r20 eor r5,r21 st Z,r2 std Z+1,r3 std Z+2,r4 std Z+3,r5 movw r18,r22 movw r20,r28 andi r18,51 andi r19,51 andi r20,51 andi r21,51 andi r22,204 andi r23,204 andi r28,204 andi r29,204 or r28,r21 or r29,r18 or r22,r19 or r23,r20 movw r18,r28 movw r20,r22 lsr r21 ror r20 ror r19 ror r18 eor r18,r28 eor r19,r29 eor r20,r22 eor r21,r23 mov r18,r1 andi r19,17 andi r20,85 andi r21,85 eor r28,r18 eor r29,r19 eor r22,r20 eor r23,r21 lsl r18 rol r19 rol r20 rol r21 eor r28,r18 eor r29,r19 eor r22,r20 eor r23,r21 std Z+4,r28 std Z+5,r29 std Z+6,r22 std Z+7,r23 ld r22,X+ ld r23,X+ ld r28,X+ ld r29,X+ ld r2,X+ ld r3,X+ ld r4,X+ ld r5,X+ lsl r2 adc r2,r1 lsl r2 adc r2,r1 swap r3 lsl r4 adc r4,r1 lsl r4 adc r4,r1 swap r5 std Z+8,r2 std Z+9,r3 std Z+10,r4 std Z+11,r5 lsl r22 adc r22,r1 lsl r22 adc r22,r1 lsl r22 adc r22,r1 lsl r23 adc r23,r1 lsl r23 adc r23,r1 lsl r28 adc r28,r1 lsl r28 adc r28,r1 lsl r28 adc r28,r1 lsl r29 adc r29,r1 lsl r29 adc r29,r1 std Z+12,r22 std Z+13,r23 std Z+14,r28 std Z+15,r29 ld r22,X+ ld r23,X+ ld r28,X+ ld r29,X+ ld r2,X+ ld r3,X+ ld r4,X+ ld r5,X+ movw r18,r2 movw r20,r4 andi r18,170 andi r19,170 andi r20,170 andi r21,170 ldi r25,85 and r2,r25 and r3,r25 and r4,r25 and r5,r25 or r2,r19 or r3,r20 or r4,r21 or r5,r18 std Z+16,r4 std Z+17,r5 std Z+18,r2 std Z+19,r3 movw r18,r22 movw r20,r28 andi r18,85 andi r19,85 andi r20,85 andi r21,85 andi r22,170 andi r23,170 andi r28,170 andi r29,170 lsl r22 rol r23 rol r28 rol r29 adc r22,r1 lsl r22 rol r23 rol r28 rol r29 adc r22,r1 lsl r22 rol r23 rol r28 rol r29 adc r22,r1 lsl r22 rol r23 rol r28 rol r29 adc r22,r1 or r22,r18 or r23,r19 or r28,r20 or r29,r21 std Z+20,r29 std Z+21,r22 std Z+22,r23 std Z+23,r28 ld r22,X+ ld r23,X+ ld r28,X+ ld r29,X+ ld r2,X+ ld r3,X+ ld r4,X+ ld r5,X+ movw r18,r2 movw r20,r4 lsr r21 ror r20 ror r19 ror r18 lsr r21 ror r20 ror r19 ror r18 eor r18,r2 eor r19,r3 eor r20,r4 eor r21,r5 andi r18,3 andi r19,3 andi r20,3 andi r21,3 eor r2,r18 eor r3,r19 eor r4,r20 eor r5,r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 eor r2,r18 eor r3,r19 eor r4,r20 eor r5,r21 movw r18,r2 movw r20,r4 lsr r21 ror r20 ror r19 ror r18 andi r18,120 andi r19,120 andi r20,120 andi r21,120 movw r14,r18 movw r16,r20 lsr r17 ror r16 ror r15 ror r14 lsr r17 ror r16 ror r15 ror r14 lsr r17 ror r16 ror r15 ror r14 lsr r17 ror r16 ror r15 ror r14 eor r14,r18 eor r15,r19 eor r16,r20 eor r17,r21 ldi r25,8 and r14,r25 and r15,r25 andi r16,8 andi r17,8 eor r18,r14 eor r19,r15 eor r20,r16 eor r21,r17 lsl r14 rol r15 rol r16 rol r17 lsl r14 rol r15 rol r16 rol r17 lsl r14 rol r15 rol r16 rol r17 lsl r14 rol r15 rol r16 rol r17 eor r18,r14 eor r19,r15 eor r20,r16 eor r21,r17 ldi r17,15 and r2,r17 and r3,r17 and r4,r17 and r5,r17 or r2,r18 or r3,r19 or r4,r20 or r5,r21 std Z+24,r2 std Z+25,r3 std Z+26,r4 std Z+27,r5 movw r18,r28 lsr r19 ror r18 lsr r19 ror r18 andi r18,48 andi r19,48 movw r2,r22 movw r4,r28 ldi r16,1 and r2,r16 and r3,r16 and r4,r16 and r5,r16 lsl r2 rol r3 rol r4 rol r5 lsl r2 rol r3 rol r4 rol r5 lsl r2 rol r3 rol r4 rol r5 or r2,r18 or r3,r19 movw r18,r28 lsl r18 rol r19 lsl r18 rol r19 andi r18,192 andi r19,192 or r2,r18 or r3,r19 movw r18,r22 andi r18,224 andi r19,224 lsr r19 ror r18 or r4,r18 or r5,r19 movw r18,r22 movw r20,r28 lsr r21 ror r20 ror r19 ror r18 andi r18,7 andi r19,7 andi r20,7 andi r21,7 or r2,r18 or r3,r19 or r4,r20 or r5,r21 andi r22,16 andi r23,16 lsl r22 rol r23 lsl r22 rol r23 lsl r22 rol r23 or r4,r22 or r5,r23 std Z+28,r2 std Z+29,r3 std Z+30,r4 std Z+31,r5 ld r22,X+ ld r23,X+ ld r28,X+ ld r29,X+ ld r2,X+ ld r3,X+ ld r4,X+ ld r5,X+ mov r0,r1 lsr r5 ror r4 ror r0 lsr r5 ror r4 ror r0 lsr r5 ror r4 ror r0 lsr r5 ror r4 ror r0 or r5,r0 std Z+32,r3 std Z+33,r2 std Z+34,r4 std Z+35,r5 mov r0,r1 lsr r23 ror r22 ror r0 lsr r23 ror r22 ror r0 lsr r23 ror r22 ror r0 lsr r23 ror r22 ror r0 or r23,r0 mov r0,r28 mov r28,r29 mov r29,r0 lsl r28 rol r29 adc r28,r1 lsl r28 rol r29 adc r28,r1 std Z+36,r22 std Z+37,r23 std Z+38,r28 std Z+39,r29 dec r24 breq 1733f adiw r30,40 rjmp 1274b 1733: pop r17 pop r16 pop r15 pop r14 pop r13 pop r12 pop r11 pop r10 pop r9 pop r8 pop r7 pop r6 pop r5 pop r4 pop r3 pop r2 pop r29 pop r28 ret .size gift128b_init, .-gift128b_init .text .global gift128b_encrypt .type gift128b_encrypt, @function gift128b_encrypt: push r28 push r29 push r2 push r3 push r4 push r5 push r6 push r7 push r8 push r9 push r10 push r11 push r12 push r13 push r14 push r15 push r17 push r23 push r22 movw r30,r24 movw r26,r20 in r28,0x3d in r29,0x3e .L__stack_usage = 19 ld r3,X+ ld r2,X+ ld r23,X+ ld r22,X+ ld r7,X+ ld r6,X+ ld r5,X+ ld r4,X+ ld r11,X+ ld r10,X+ ld r9,X+ ld r8,X+ ld r15,X+ ld r14,X+ ld r13,X+ ld r12,X+ movw r26,r30 ldi r30,lo8(table_0) ldi r31,hi8(table_0) #if defined(RAMPZ) ldi r24,hh8(table_0) in r0,_SFR_IO_ADDR(RAMPZ) push r0 out _SFR_IO_ADDR(RAMPZ),r24 #endif rcall 27f rcall 27f rcall 27f rcall 27f rcall 27f rcall 27f rcall 27f rcall 27f rjmp 765f 27: mov r0,r22 and r0,r8 eor r4,r0 mov r0,r23 and r0,r9 eor r5,r0 mov r0,r2 and r0,r10 eor r6,r0 mov r0,r3 and r0,r11 eor r7,r0 mov r0,r4 and r0,r12 eor r22,r0 mov r0,r5 and r0,r13 eor r23,r0 mov r0,r6 and r0,r14 eor r2,r0 mov r0,r7 and r0,r15 eor r3,r0 mov r0,r22 or r0,r4 eor r8,r0 mov r0,r23 or r0,r5 eor r9,r0 mov r0,r2 or r0,r6 eor r10,r0 mov r0,r3 or r0,r7 eor r11,r0 eor r12,r8 eor r13,r9 eor r14,r10 eor r15,r11 eor r4,r12 eor r5,r13 eor r6,r14 eor r7,r15 com r12 com r13 com r14 com r15 mov r0,r22 and r0,r4 eor r8,r0 mov r0,r23 and r0,r5 eor r9,r0 mov r0,r2 and r0,r6 eor r10,r0 mov r0,r3 and r0,r7 eor r11,r0 movw r18,r4 movw r20,r6 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 andi r18,204 andi r19,204 andi r20,204 andi r21,204 lsr r7 ror r6 ror r5 ror r4 lsr r7 ror r6 ror r5 ror r4 ldi r25,51 and r4,r25 and r5,r25 and r6,r25 and r7,r25 or r4,r18 or r5,r19 or r6,r20 or r7,r21 movw r18,r8 movw r20,r10 lsl r18 rol r19 rol r20 rol r21 andi r18,238 andi r19,238 andi r20,238 andi r21,238 lsr r11 ror r10 ror r9 ror r8 lsr r11 ror r10 ror r9 ror r8 lsr r11 ror r10 ror r9 ror r8 ldi r24,17 and r8,r24 and r9,r24 and r10,r24 and r11,r24 or r8,r18 or r9,r19 or r10,r20 or r11,r21 movw r18,r12 movw r20,r14 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 andi r18,136 andi r19,136 andi r20,136 andi r21,136 lsr r15 ror r14 ror r13 ror r12 ldi r17,119 and r12,r17 and r13,r17 and r14,r17 and r15,r17 or r12,r18 or r13,r19 or r14,r20 or r15,r21 ld r18,X+ ld r19,X+ ld r20,X+ ld r21,X+ eor r4,r18 eor r5,r19 eor r6,r20 eor r7,r21 ld r18,X+ ld r19,X+ ld r20,X+ ld r21,X+ eor r8,r18 eor r9,r19 eor r10,r20 eor r11,r21 #if defined(RAMPZ) elpm r18,Z #elif defined(__AVR_HAVE_LPMX__) lpm r18,Z #elif defined(__AVR_TINY__) ld r18,Z #else lpm mov r18,r0 #endif inc r30 #if defined(RAMPZ) elpm r19,Z #elif defined(__AVR_HAVE_LPMX__) lpm r19,Z #elif defined(__AVR_TINY__) ld r19,Z #else lpm mov r19,r0 #endif inc r30 #if defined(RAMPZ) elpm r20,Z #elif defined(__AVR_HAVE_LPMX__) lpm r20,Z #elif defined(__AVR_TINY__) ld r20,Z #else lpm mov r20,r0 #endif inc r30 #if defined(RAMPZ) elpm r21,Z #elif defined(__AVR_HAVE_LPMX__) lpm r21,Z #elif defined(__AVR_TINY__) ld r21,Z #else lpm mov r21,r0 #endif inc r30 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 mov r0,r12 and r0,r8 eor r4,r0 mov r0,r13 and r0,r9 eor r5,r0 mov r0,r14 and r0,r10 eor r6,r0 mov r0,r15 and r0,r11 eor r7,r0 mov r0,r4 and r0,r22 eor r12,r0 mov r0,r5 and r0,r23 eor r13,r0 mov r0,r6 and r0,r2 eor r14,r0 mov r0,r7 and r0,r3 eor r15,r0 mov r0,r12 or r0,r4 eor r8,r0 mov r0,r13 or r0,r5 eor r9,r0 mov r0,r14 or r0,r6 eor r10,r0 mov r0,r15 or r0,r7 eor r11,r0 eor r22,r8 eor r23,r9 eor r2,r10 eor r3,r11 eor r4,r22 eor r5,r23 eor r6,r2 eor r7,r3 com r22 com r23 com r2 com r3 mov r0,r12 and r0,r4 eor r8,r0 mov r0,r13 and r0,r5 eor r9,r0 mov r0,r14 and r0,r6 eor r10,r0 mov r0,r15 and r0,r7 eor r11,r0 mov r0,r1 lsr r23 ror r22 ror r0 lsr r23 ror r22 ror r0 lsr r23 ror r22 ror r0 lsr r23 ror r22 ror r0 or r23,r0 mov r0,r1 lsr r3 ror r2 ror r0 lsr r3 ror r2 ror r0 lsr r3 ror r2 ror r0 lsr r3 ror r2 ror r0 or r3,r0 mov r0,r5 mov r5,r4 mov r4,r0 mov r0,r7 mov r7,r6 mov r6,r0 lsl r8 rol r9 adc r8,r1 lsl r8 rol r9 adc r8,r1 lsl r8 rol r9 adc r8,r1 lsl r8 rol r9 adc r8,r1 lsl r10 rol r11 adc r10,r1 lsl r10 rol r11 adc r10,r1 lsl r10 rol r11 adc r10,r1 lsl r10 rol r11 adc r10,r1 ld r18,X+ ld r19,X+ ld r20,X+ ld r21,X+ eor r4,r18 eor r5,r19 eor r6,r20 eor r7,r21 ld r18,X+ ld r19,X+ ld r20,X+ ld r21,X+ eor r8,r18 eor r9,r19 eor r10,r20 eor r11,r21 #if defined(RAMPZ) elpm r18,Z #elif defined(__AVR_HAVE_LPMX__) lpm r18,Z #elif defined(__AVR_TINY__) ld r18,Z #else lpm mov r18,r0 #endif inc r30 #if defined(RAMPZ) elpm r19,Z #elif defined(__AVR_HAVE_LPMX__) lpm r19,Z #elif defined(__AVR_TINY__) ld r19,Z #else lpm mov r19,r0 #endif inc r30 #if defined(RAMPZ) elpm r20,Z #elif defined(__AVR_HAVE_LPMX__) lpm r20,Z #elif defined(__AVR_TINY__) ld r20,Z #else lpm mov r20,r0 #endif inc r30 #if defined(RAMPZ) elpm r21,Z #elif defined(__AVR_HAVE_LPMX__) lpm r21,Z #elif defined(__AVR_TINY__) ld r21,Z #else lpm mov r21,r0 #endif inc r30 eor r12,r18 eor r13,r19 eor r14,r20 eor r15,r21 mov r0,r22 and r0,r8 eor r4,r0 mov r0,r23 and r0,r9 eor r5,r0 mov r0,r2 and r0,r10 eor r6,r0 mov r0,r3 and r0,r11 eor r7,r0 mov r0,r4 and r0,r12 eor r22,r0 mov r0,r5 and r0,r13 eor r23,r0 mov r0,r6 and r0,r14 eor r2,r0 mov r0,r7 and r0,r15 eor r3,r0 mov r0,r22 or r0,r4 eor r8,r0 mov r0,r23 or r0,r5 eor r9,r0 mov r0,r2 or r0,r6 eor r10,r0 mov r0,r3 or r0,r7 eor r11,r0 eor r12,r8 eor r13,r9 eor r14,r10 eor r15,r11 eor r4,r12 eor r5,r13 eor r6,r14 eor r7,r15 com r12 com r13 com r14 com r15 mov r0,r22 and r0,r4 eor r8,r0 mov r0,r23 and r0,r5 eor r9,r0 mov r0,r2 and r0,r6 eor r10,r0 mov r0,r3 and r0,r7 eor r11,r0 movw r18,r4 movw r20,r6 lsr r21 ror r20 ror r19 ror r18 eor r18,r4 eor r19,r5 eor r20,r6 eor r21,r7 andi r18,85 andi r19,85 andi r20,85 andi r21,85 eor r4,r18 eor r5,r19 eor r6,r20 eor r7,r21 lsl r18 rol r19 rol r20 rol r21 eor r4,r18 eor r5,r19 eor r6,r20 eor r7,r21 mov r0,r10 mov r10,r8 mov r8,r0 mov r0,r11 mov r11,r9 mov r9,r0 movw r18,r8 movw r20,r10 lsr r21 ror r20 ror r19 ror r18 eor r18,r8 eor r19,r9 andi r18,85 andi r19,85 eor r8,r18 eor r9,r19 mov r20,r1 mov r21,r1 lsl r18 rol r19 rol r20 rol r21 eor r8,r18 eor r9,r19 eor r10,r20 eor r11,r21 mov r0,r14 mov r14,r12 mov r12,r0 mov r0,r15 mov r15,r13 mov r13,r0 movw r18,r14 lsr r19 ror r18 eor r18,r14 eor r19,r15 andi r18,85 andi r19,85 eor r14,r18 eor r15,r19 lsl r18 rol r19 eor r14,r18 eor r15,r19 ld r18,X+ ld r19,X+ ld r20,X+ ld r21,X+ eor r4,r18 eor r5,r19 eor r6,r20 eor r7,r21 ld r18,X+ ld r19,X+ ld r20,X+ ld r21,X+ eor r8,r18 eor r9,r19 eor r10,r20 eor r11,r21 #if defined(RAMPZ) elpm r18,Z #elif defined(__AVR_HAVE_LPMX__) lpm r18,Z #elif defined(__AVR_TINY__) ld r18,Z #else lpm mov r18,r0 #endif inc r30 #if defined(RAMPZ) elpm r19,Z #elif defined(__AVR_HAVE_LPMX__) lpm r19,Z #elif defined(__AVR_TINY__) ld r19,Z #else lpm mov r19,r0 #endif inc r30 #if defined(RAMPZ) elpm r20,Z #elif defined(__AVR_HAVE_LPMX__) lpm r20,Z #elif defined(__AVR_TINY__) ld r20,Z #else lpm mov r20,r0 #endif inc r30 #if defined(RAMPZ) elpm r21,Z #elif defined(__AVR_HAVE_LPMX__) lpm r21,Z #elif defined(__AVR_TINY__) ld r21,Z #else lpm mov r21,r0 #endif inc r30 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 mov r0,r12 and r0,r8 eor r4,r0 mov r0,r13 and r0,r9 eor r5,r0 mov r0,r14 and r0,r10 eor r6,r0 mov r0,r15 and r0,r11 eor r7,r0 mov r0,r4 and r0,r22 eor r12,r0 mov r0,r5 and r0,r23 eor r13,r0 mov r0,r6 and r0,r2 eor r14,r0 mov r0,r7 and r0,r3 eor r15,r0 mov r0,r12 or r0,r4 eor r8,r0 mov r0,r13 or r0,r5 eor r9,r0 mov r0,r14 or r0,r6 eor r10,r0 mov r0,r15 or r0,r7 eor r11,r0 eor r22,r8 eor r23,r9 eor r2,r10 eor r3,r11 eor r4,r22 eor r5,r23 eor r6,r2 eor r7,r3 com r22 com r23 com r2 com r3 mov r0,r12 and r0,r4 eor r8,r0 mov r0,r13 and r0,r5 eor r9,r0 mov r0,r14 and r0,r6 eor r10,r0 mov r0,r15 and r0,r7 eor r11,r0 lsl r22 adc r22,r1 lsl r22 adc r22,r1 lsl r23 adc r23,r1 lsl r23 adc r23,r1 lsl r2 adc r2,r1 lsl r2 adc r2,r1 lsl r3 adc r3,r1 lsl r3 adc r3,r1 swap r4 swap r5 swap r6 swap r7 mov r0,r1 lsr r8 ror r0 lsr r8 ror r0 or r8,r0 mov r0,r1 lsr r9 ror r0 lsr r9 ror r0 or r9,r0 mov r0,r1 lsr r10 ror r0 lsr r10 ror r0 or r10,r0 mov r0,r1 lsr r11 ror r0 lsr r11 ror r0 or r11,r0 ld r18,X+ ld r19,X+ ld r20,X+ ld r21,X+ eor r4,r18 eor r5,r19 eor r6,r20 eor r7,r21 ld r18,X+ ld r19,X+ ld r20,X+ ld r21,X+ eor r8,r18 eor r9,r19 eor r10,r20 eor r11,r21 #if defined(RAMPZ) elpm r18,Z #elif defined(__AVR_HAVE_LPMX__) lpm r18,Z #elif defined(__AVR_TINY__) ld r18,Z #else lpm mov r18,r0 #endif inc r30 #if defined(RAMPZ) elpm r19,Z #elif defined(__AVR_HAVE_LPMX__) lpm r19,Z #elif defined(__AVR_TINY__) ld r19,Z #else lpm mov r19,r0 #endif inc r30 #if defined(RAMPZ) elpm r20,Z #elif defined(__AVR_HAVE_LPMX__) lpm r20,Z #elif defined(__AVR_TINY__) ld r20,Z #else lpm mov r20,r0 #endif inc r30 #if defined(RAMPZ) elpm r21,Z #elif defined(__AVR_HAVE_LPMX__) lpm r21,Z #elif defined(__AVR_TINY__) ld r21,Z #else lpm mov r21,r0 #endif inc r30 eor r12,r18 eor r13,r19 eor r14,r20 eor r15,r21 mov r0,r22 and r0,r8 eor r4,r0 mov r0,r23 and r0,r9 eor r5,r0 mov r0,r2 and r0,r10 eor r6,r0 mov r0,r3 and r0,r11 eor r7,r0 mov r0,r4 and r0,r12 eor r22,r0 mov r0,r5 and r0,r13 eor r23,r0 mov r0,r6 and r0,r14 eor r2,r0 mov r0,r7 and r0,r15 eor r3,r0 mov r0,r22 or r0,r4 eor r8,r0 mov r0,r23 or r0,r5 eor r9,r0 mov r0,r2 or r0,r6 eor r10,r0 mov r0,r3 or r0,r7 eor r11,r0 eor r12,r8 eor r13,r9 eor r14,r10 eor r15,r11 eor r4,r12 eor r5,r13 eor r6,r14 eor r7,r15 com r12 com r13 com r14 com r15 mov r0,r22 and r0,r4 eor r8,r0 mov r0,r23 and r0,r5 eor r9,r0 mov r0,r2 and r0,r6 eor r10,r0 mov r0,r3 and r0,r7 eor r11,r0 mov r0,r6 mov r6,r4 mov r4,r0 mov r0,r7 mov r7,r5 mov r5,r0 mov r0,r8 mov r8,r9 mov r9,r10 mov r10,r11 mov r11,r0 mov r0,r15 mov r15,r14 mov r14,r13 mov r13,r12 mov r12,r0 ld r18,X+ ld r19,X+ ld r20,X+ ld r21,X+ eor r4,r18 eor r5,r19 eor r6,r20 eor r7,r21 ld r18,X+ ld r19,X+ ld r20,X+ ld r21,X+ eor r8,r18 eor r9,r19 eor r10,r20 eor r11,r21 #if defined(RAMPZ) elpm r18,Z #elif defined(__AVR_HAVE_LPMX__) lpm r18,Z #elif defined(__AVR_TINY__) ld r18,Z #else lpm mov r18,r0 #endif inc r30 #if defined(RAMPZ) elpm r19,Z #elif defined(__AVR_HAVE_LPMX__) lpm r19,Z #elif defined(__AVR_TINY__) ld r19,Z #else lpm mov r19,r0 #endif inc r30 #if defined(RAMPZ) elpm r20,Z #elif defined(__AVR_HAVE_LPMX__) lpm r20,Z #elif defined(__AVR_TINY__) ld r20,Z #else lpm mov r20,r0 #endif inc r30 #if defined(RAMPZ) elpm r21,Z #elif defined(__AVR_HAVE_LPMX__) lpm r21,Z #elif defined(__AVR_TINY__) ld r21,Z #else lpm mov r21,r0 #endif inc r30 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 eor r22,r12 eor r23,r13 eor r2,r14 eor r3,r15 eor r12,r22 eor r13,r23 eor r14,r2 eor r15,r3 eor r22,r12 eor r23,r13 eor r2,r14 eor r3,r15 ret 765: #if defined(RAMPZ) pop r0 out _SFR_IO_ADDR(RAMPZ),r0 #endif ldd r26,Y+1 ldd r27,Y+2 st X+,r3 st X+,r2 st X+,r23 st X+,r22 st X+,r7 st X+,r6 st X+,r5 st X+,r4 st X+,r11 st X+,r10 st X+,r9 st X+,r8 st X+,r15 st X+,r14 st X+,r13 st X+,r12 pop r0 pop r0 pop r17 pop r15 pop r14 pop r13 pop r12 pop r11 pop r10 pop r9 pop r8 pop r7 pop r6 pop r5 pop r4 pop r3 pop r2 pop r29 pop r28 ret .size gift128b_encrypt, .-gift128b_encrypt .text .global gift128b_encrypt_preloaded .type gift128b_encrypt_preloaded, @function gift128b_encrypt_preloaded: push r28 push r29 push r2 push r3 push r4 push r5 push r6 push r7 push r8 push r9 push r10 push r11 push r12 push r13 push r14 push r15 push r17 push r23 push r22 movw r30,r24 movw r26,r20 in r28,0x3d in r29,0x3e .L__stack_usage = 19 ld r22,X+ ld r23,X+ ld r2,X+ ld r3,X+ ld r4,X+ ld r5,X+ ld r6,X+ ld r7,X+ ld r8,X+ ld r9,X+ ld r10,X+ ld r11,X+ ld r12,X+ ld r13,X+ ld r14,X+ ld r15,X+ movw r26,r30 ldi r30,lo8(table_0) ldi r31,hi8(table_0) #if defined(RAMPZ) ldi r24,hh8(table_0) in r0,_SFR_IO_ADDR(RAMPZ) push r0 out _SFR_IO_ADDR(RAMPZ),r24 #endif rcall 27f rcall 27f rcall 27f rcall 27f rcall 27f rcall 27f rcall 27f rcall 27f rjmp 765f 27: mov r0,r22 and r0,r8 eor r4,r0 mov r0,r23 and r0,r9 eor r5,r0 mov r0,r2 and r0,r10 eor r6,r0 mov r0,r3 and r0,r11 eor r7,r0 mov r0,r4 and r0,r12 eor r22,r0 mov r0,r5 and r0,r13 eor r23,r0 mov r0,r6 and r0,r14 eor r2,r0 mov r0,r7 and r0,r15 eor r3,r0 mov r0,r22 or r0,r4 eor r8,r0 mov r0,r23 or r0,r5 eor r9,r0 mov r0,r2 or r0,r6 eor r10,r0 mov r0,r3 or r0,r7 eor r11,r0 eor r12,r8 eor r13,r9 eor r14,r10 eor r15,r11 eor r4,r12 eor r5,r13 eor r6,r14 eor r7,r15 com r12 com r13 com r14 com r15 mov r0,r22 and r0,r4 eor r8,r0 mov r0,r23 and r0,r5 eor r9,r0 mov r0,r2 and r0,r6 eor r10,r0 mov r0,r3 and r0,r7 eor r11,r0 movw r18,r4 movw r20,r6 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 andi r18,204 andi r19,204 andi r20,204 andi r21,204 lsr r7 ror r6 ror r5 ror r4 lsr r7 ror r6 ror r5 ror r4 ldi r25,51 and r4,r25 and r5,r25 and r6,r25 and r7,r25 or r4,r18 or r5,r19 or r6,r20 or r7,r21 movw r18,r8 movw r20,r10 lsl r18 rol r19 rol r20 rol r21 andi r18,238 andi r19,238 andi r20,238 andi r21,238 lsr r11 ror r10 ror r9 ror r8 lsr r11 ror r10 ror r9 ror r8 lsr r11 ror r10 ror r9 ror r8 ldi r24,17 and r8,r24 and r9,r24 and r10,r24 and r11,r24 or r8,r18 or r9,r19 or r10,r20 or r11,r21 movw r18,r12 movw r20,r14 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 andi r18,136 andi r19,136 andi r20,136 andi r21,136 lsr r15 ror r14 ror r13 ror r12 ldi r17,119 and r12,r17 and r13,r17 and r14,r17 and r15,r17 or r12,r18 or r13,r19 or r14,r20 or r15,r21 ld r18,X+ ld r19,X+ ld r20,X+ ld r21,X+ eor r4,r18 eor r5,r19 eor r6,r20 eor r7,r21 ld r18,X+ ld r19,X+ ld r20,X+ ld r21,X+ eor r8,r18 eor r9,r19 eor r10,r20 eor r11,r21 #if defined(RAMPZ) elpm r18,Z #elif defined(__AVR_HAVE_LPMX__) lpm r18,Z #elif defined(__AVR_TINY__) ld r18,Z #else lpm mov r18,r0 #endif inc r30 #if defined(RAMPZ) elpm r19,Z #elif defined(__AVR_HAVE_LPMX__) lpm r19,Z #elif defined(__AVR_TINY__) ld r19,Z #else lpm mov r19,r0 #endif inc r30 #if defined(RAMPZ) elpm r20,Z #elif defined(__AVR_HAVE_LPMX__) lpm r20,Z #elif defined(__AVR_TINY__) ld r20,Z #else lpm mov r20,r0 #endif inc r30 #if defined(RAMPZ) elpm r21,Z #elif defined(__AVR_HAVE_LPMX__) lpm r21,Z #elif defined(__AVR_TINY__) ld r21,Z #else lpm mov r21,r0 #endif inc r30 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 mov r0,r12 and r0,r8 eor r4,r0 mov r0,r13 and r0,r9 eor r5,r0 mov r0,r14 and r0,r10 eor r6,r0 mov r0,r15 and r0,r11 eor r7,r0 mov r0,r4 and r0,r22 eor r12,r0 mov r0,r5 and r0,r23 eor r13,r0 mov r0,r6 and r0,r2 eor r14,r0 mov r0,r7 and r0,r3 eor r15,r0 mov r0,r12 or r0,r4 eor r8,r0 mov r0,r13 or r0,r5 eor r9,r0 mov r0,r14 or r0,r6 eor r10,r0 mov r0,r15 or r0,r7 eor r11,r0 eor r22,r8 eor r23,r9 eor r2,r10 eor r3,r11 eor r4,r22 eor r5,r23 eor r6,r2 eor r7,r3 com r22 com r23 com r2 com r3 mov r0,r12 and r0,r4 eor r8,r0 mov r0,r13 and r0,r5 eor r9,r0 mov r0,r14 and r0,r6 eor r10,r0 mov r0,r15 and r0,r7 eor r11,r0 mov r0,r1 lsr r23 ror r22 ror r0 lsr r23 ror r22 ror r0 lsr r23 ror r22 ror r0 lsr r23 ror r22 ror r0 or r23,r0 mov r0,r1 lsr r3 ror r2 ror r0 lsr r3 ror r2 ror r0 lsr r3 ror r2 ror r0 lsr r3 ror r2 ror r0 or r3,r0 mov r0,r5 mov r5,r4 mov r4,r0 mov r0,r7 mov r7,r6 mov r6,r0 lsl r8 rol r9 adc r8,r1 lsl r8 rol r9 adc r8,r1 lsl r8 rol r9 adc r8,r1 lsl r8 rol r9 adc r8,r1 lsl r10 rol r11 adc r10,r1 lsl r10 rol r11 adc r10,r1 lsl r10 rol r11 adc r10,r1 lsl r10 rol r11 adc r10,r1 ld r18,X+ ld r19,X+ ld r20,X+ ld r21,X+ eor r4,r18 eor r5,r19 eor r6,r20 eor r7,r21 ld r18,X+ ld r19,X+ ld r20,X+ ld r21,X+ eor r8,r18 eor r9,r19 eor r10,r20 eor r11,r21 #if defined(RAMPZ) elpm r18,Z #elif defined(__AVR_HAVE_LPMX__) lpm r18,Z #elif defined(__AVR_TINY__) ld r18,Z #else lpm mov r18,r0 #endif inc r30 #if defined(RAMPZ) elpm r19,Z #elif defined(__AVR_HAVE_LPMX__) lpm r19,Z #elif defined(__AVR_TINY__) ld r19,Z #else lpm mov r19,r0 #endif inc r30 #if defined(RAMPZ) elpm r20,Z #elif defined(__AVR_HAVE_LPMX__) lpm r20,Z #elif defined(__AVR_TINY__) ld r20,Z #else lpm mov r20,r0 #endif inc r30 #if defined(RAMPZ) elpm r21,Z #elif defined(__AVR_HAVE_LPMX__) lpm r21,Z #elif defined(__AVR_TINY__) ld r21,Z #else lpm mov r21,r0 #endif inc r30 eor r12,r18 eor r13,r19 eor r14,r20 eor r15,r21 mov r0,r22 and r0,r8 eor r4,r0 mov r0,r23 and r0,r9 eor r5,r0 mov r0,r2 and r0,r10 eor r6,r0 mov r0,r3 and r0,r11 eor r7,r0 mov r0,r4 and r0,r12 eor r22,r0 mov r0,r5 and r0,r13 eor r23,r0 mov r0,r6 and r0,r14 eor r2,r0 mov r0,r7 and r0,r15 eor r3,r0 mov r0,r22 or r0,r4 eor r8,r0 mov r0,r23 or r0,r5 eor r9,r0 mov r0,r2 or r0,r6 eor r10,r0 mov r0,r3 or r0,r7 eor r11,r0 eor r12,r8 eor r13,r9 eor r14,r10 eor r15,r11 eor r4,r12 eor r5,r13 eor r6,r14 eor r7,r15 com r12 com r13 com r14 com r15 mov r0,r22 and r0,r4 eor r8,r0 mov r0,r23 and r0,r5 eor r9,r0 mov r0,r2 and r0,r6 eor r10,r0 mov r0,r3 and r0,r7 eor r11,r0 movw r18,r4 movw r20,r6 lsr r21 ror r20 ror r19 ror r18 eor r18,r4 eor r19,r5 eor r20,r6 eor r21,r7 andi r18,85 andi r19,85 andi r20,85 andi r21,85 eor r4,r18 eor r5,r19 eor r6,r20 eor r7,r21 lsl r18 rol r19 rol r20 rol r21 eor r4,r18 eor r5,r19 eor r6,r20 eor r7,r21 mov r0,r10 mov r10,r8 mov r8,r0 mov r0,r11 mov r11,r9 mov r9,r0 movw r18,r8 movw r20,r10 lsr r21 ror r20 ror r19 ror r18 eor r18,r8 eor r19,r9 andi r18,85 andi r19,85 eor r8,r18 eor r9,r19 mov r20,r1 mov r21,r1 lsl r18 rol r19 rol r20 rol r21 eor r8,r18 eor r9,r19 eor r10,r20 eor r11,r21 mov r0,r14 mov r14,r12 mov r12,r0 mov r0,r15 mov r15,r13 mov r13,r0 movw r18,r14 lsr r19 ror r18 eor r18,r14 eor r19,r15 andi r18,85 andi r19,85 eor r14,r18 eor r15,r19 lsl r18 rol r19 eor r14,r18 eor r15,r19 ld r18,X+ ld r19,X+ ld r20,X+ ld r21,X+ eor r4,r18 eor r5,r19 eor r6,r20 eor r7,r21 ld r18,X+ ld r19,X+ ld r20,X+ ld r21,X+ eor r8,r18 eor r9,r19 eor r10,r20 eor r11,r21 #if defined(RAMPZ) elpm r18,Z #elif defined(__AVR_HAVE_LPMX__) lpm r18,Z #elif defined(__AVR_TINY__) ld r18,Z #else lpm mov r18,r0 #endif inc r30 #if defined(RAMPZ) elpm r19,Z #elif defined(__AVR_HAVE_LPMX__) lpm r19,Z #elif defined(__AVR_TINY__) ld r19,Z #else lpm mov r19,r0 #endif inc r30 #if defined(RAMPZ) elpm r20,Z #elif defined(__AVR_HAVE_LPMX__) lpm r20,Z #elif defined(__AVR_TINY__) ld r20,Z #else lpm mov r20,r0 #endif inc r30 #if defined(RAMPZ) elpm r21,Z #elif defined(__AVR_HAVE_LPMX__) lpm r21,Z #elif defined(__AVR_TINY__) ld r21,Z #else lpm mov r21,r0 #endif inc r30 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 mov r0,r12 and r0,r8 eor r4,r0 mov r0,r13 and r0,r9 eor r5,r0 mov r0,r14 and r0,r10 eor r6,r0 mov r0,r15 and r0,r11 eor r7,r0 mov r0,r4 and r0,r22 eor r12,r0 mov r0,r5 and r0,r23 eor r13,r0 mov r0,r6 and r0,r2 eor r14,r0 mov r0,r7 and r0,r3 eor r15,r0 mov r0,r12 or r0,r4 eor r8,r0 mov r0,r13 or r0,r5 eor r9,r0 mov r0,r14 or r0,r6 eor r10,r0 mov r0,r15 or r0,r7 eor r11,r0 eor r22,r8 eor r23,r9 eor r2,r10 eor r3,r11 eor r4,r22 eor r5,r23 eor r6,r2 eor r7,r3 com r22 com r23 com r2 com r3 mov r0,r12 and r0,r4 eor r8,r0 mov r0,r13 and r0,r5 eor r9,r0 mov r0,r14 and r0,r6 eor r10,r0 mov r0,r15 and r0,r7 eor r11,r0 lsl r22 adc r22,r1 lsl r22 adc r22,r1 lsl r23 adc r23,r1 lsl r23 adc r23,r1 lsl r2 adc r2,r1 lsl r2 adc r2,r1 lsl r3 adc r3,r1 lsl r3 adc r3,r1 swap r4 swap r5 swap r6 swap r7 mov r0,r1 lsr r8 ror r0 lsr r8 ror r0 or r8,r0 mov r0,r1 lsr r9 ror r0 lsr r9 ror r0 or r9,r0 mov r0,r1 lsr r10 ror r0 lsr r10 ror r0 or r10,r0 mov r0,r1 lsr r11 ror r0 lsr r11 ror r0 or r11,r0 ld r18,X+ ld r19,X+ ld r20,X+ ld r21,X+ eor r4,r18 eor r5,r19 eor r6,r20 eor r7,r21 ld r18,X+ ld r19,X+ ld r20,X+ ld r21,X+ eor r8,r18 eor r9,r19 eor r10,r20 eor r11,r21 #if defined(RAMPZ) elpm r18,Z #elif defined(__AVR_HAVE_LPMX__) lpm r18,Z #elif defined(__AVR_TINY__) ld r18,Z #else lpm mov r18,r0 #endif inc r30 #if defined(RAMPZ) elpm r19,Z #elif defined(__AVR_HAVE_LPMX__) lpm r19,Z #elif defined(__AVR_TINY__) ld r19,Z #else lpm mov r19,r0 #endif inc r30 #if defined(RAMPZ) elpm r20,Z #elif defined(__AVR_HAVE_LPMX__) lpm r20,Z #elif defined(__AVR_TINY__) ld r20,Z #else lpm mov r20,r0 #endif inc r30 #if defined(RAMPZ) elpm r21,Z #elif defined(__AVR_HAVE_LPMX__) lpm r21,Z #elif defined(__AVR_TINY__) ld r21,Z #else lpm mov r21,r0 #endif inc r30 eor r12,r18 eor r13,r19 eor r14,r20 eor r15,r21 mov r0,r22 and r0,r8 eor r4,r0 mov r0,r23 and r0,r9 eor r5,r0 mov r0,r2 and r0,r10 eor r6,r0 mov r0,r3 and r0,r11 eor r7,r0 mov r0,r4 and r0,r12 eor r22,r0 mov r0,r5 and r0,r13 eor r23,r0 mov r0,r6 and r0,r14 eor r2,r0 mov r0,r7 and r0,r15 eor r3,r0 mov r0,r22 or r0,r4 eor r8,r0 mov r0,r23 or r0,r5 eor r9,r0 mov r0,r2 or r0,r6 eor r10,r0 mov r0,r3 or r0,r7 eor r11,r0 eor r12,r8 eor r13,r9 eor r14,r10 eor r15,r11 eor r4,r12 eor r5,r13 eor r6,r14 eor r7,r15 com r12 com r13 com r14 com r15 mov r0,r22 and r0,r4 eor r8,r0 mov r0,r23 and r0,r5 eor r9,r0 mov r0,r2 and r0,r6 eor r10,r0 mov r0,r3 and r0,r7 eor r11,r0 mov r0,r6 mov r6,r4 mov r4,r0 mov r0,r7 mov r7,r5 mov r5,r0 mov r0,r8 mov r8,r9 mov r9,r10 mov r10,r11 mov r11,r0 mov r0,r15 mov r15,r14 mov r14,r13 mov r13,r12 mov r12,r0 ld r18,X+ ld r19,X+ ld r20,X+ ld r21,X+ eor r4,r18 eor r5,r19 eor r6,r20 eor r7,r21 ld r18,X+ ld r19,X+ ld r20,X+ ld r21,X+ eor r8,r18 eor r9,r19 eor r10,r20 eor r11,r21 #if defined(RAMPZ) elpm r18,Z #elif defined(__AVR_HAVE_LPMX__) lpm r18,Z #elif defined(__AVR_TINY__) ld r18,Z #else lpm mov r18,r0 #endif inc r30 #if defined(RAMPZ) elpm r19,Z #elif defined(__AVR_HAVE_LPMX__) lpm r19,Z #elif defined(__AVR_TINY__) ld r19,Z #else lpm mov r19,r0 #endif inc r30 #if defined(RAMPZ) elpm r20,Z #elif defined(__AVR_HAVE_LPMX__) lpm r20,Z #elif defined(__AVR_TINY__) ld r20,Z #else lpm mov r20,r0 #endif inc r30 #if defined(RAMPZ) elpm r21,Z #elif defined(__AVR_HAVE_LPMX__) lpm r21,Z #elif defined(__AVR_TINY__) ld r21,Z #else lpm mov r21,r0 #endif inc r30 eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 eor r22,r12 eor r23,r13 eor r2,r14 eor r3,r15 eor r12,r22 eor r13,r23 eor r14,r2 eor r15,r3 eor r22,r12 eor r23,r13 eor r2,r14 eor r3,r15 ret 765: #if defined(RAMPZ) pop r0 out _SFR_IO_ADDR(RAMPZ),r0 #endif ldd r26,Y+1 ldd r27,Y+2 st X+,r22 st X+,r23 st X+,r2 st X+,r3 st X+,r4 st X+,r5 st X+,r6 st X+,r7 st X+,r8 st X+,r9 st X+,r10 st X+,r11 st X+,r12 st X+,r13 st X+,r14 st X+,r15 pop r0 pop r0 pop r17 pop r15 pop r14 pop r13 pop r12 pop r11 pop r10 pop r9 pop r8 pop r7 pop r6 pop r5 pop r4 pop r3 pop r2 pop r29 pop r28 ret .size gift128b_encrypt_preloaded, .-gift128b_encrypt_preloaded .text .global gift128b_decrypt .type gift128b_decrypt, @function gift128b_decrypt: push r28 push r29 push r2 push r3 push r4 push r5 push r6 push r7 push r8 push r9 push r10 push r11 push r12 push r13 push r14 push r15 push r17 push r23 push r22 movw r30,r24 movw r26,r20 in r28,0x3d in r29,0x3e .L__stack_usage = 19 ld r3,X+ ld r2,X+ ld r23,X+ ld r22,X+ ld r7,X+ ld r6,X+ ld r5,X+ ld r4,X+ ld r11,X+ ld r10,X+ ld r9,X+ ld r8,X+ ld r15,X+ ld r14,X+ ld r13,X+ ld r12,X+ movw r26,r30 subi r26,192 sbci r27,254 ldi r30,lo8(table_0) ldi r31,hi8(table_0) #if defined(RAMPZ) ldi r24,hh8(table_0) in r0,_SFR_IO_ADDR(RAMPZ) push r0 out _SFR_IO_ADDR(RAMPZ),r24 #endif ldi r30,160 rcall 30f rcall 30f rcall 30f rcall 30f rcall 30f rcall 30f rcall 30f rcall 30f rjmp 768f 30: eor r22,r12 eor r23,r13 eor r2,r14 eor r3,r15 eor r12,r22 eor r13,r23 eor r14,r2 eor r15,r3 eor r22,r12 eor r23,r13 eor r2,r14 eor r3,r15 dec r30 #if defined(RAMPZ) elpm r21,Z #elif defined(__AVR_HAVE_LPMX__) lpm r21,Z #elif defined(__AVR_TINY__) ld r21,Z #else lpm mov r21,r0 #endif dec r30 #if defined(RAMPZ) elpm r20,Z #elif defined(__AVR_HAVE_LPMX__) lpm r20,Z #elif defined(__AVR_TINY__) ld r20,Z #else lpm mov r20,r0 #endif dec r30 #if defined(RAMPZ) elpm r19,Z #elif defined(__AVR_HAVE_LPMX__) lpm r19,Z #elif defined(__AVR_TINY__) ld r19,Z #else lpm mov r19,r0 #endif dec r30 #if defined(RAMPZ) elpm r18,Z #elif defined(__AVR_HAVE_LPMX__) lpm r18,Z #elif defined(__AVR_TINY__) ld r18,Z #else lpm mov r18,r0 #endif eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 ld r21,-X ld r20,-X ld r19,-X ld r18,-X eor r8,r18 eor r9,r19 eor r10,r20 eor r11,r21 ld r21,-X ld r20,-X ld r19,-X ld r18,-X eor r4,r18 eor r5,r19 eor r6,r20 eor r7,r21 mov r0,r6 mov r6,r4 mov r4,r0 mov r0,r7 mov r7,r5 mov r5,r0 mov r0,r11 mov r11,r10 mov r10,r9 mov r9,r8 mov r8,r0 mov r0,r12 mov r12,r13 mov r13,r14 mov r14,r15 mov r15,r0 mov r0,r22 and r0,r4 eor r8,r0 mov r0,r23 and r0,r5 eor r9,r0 mov r0,r2 and r0,r6 eor r10,r0 mov r0,r3 and r0,r7 eor r11,r0 com r12 com r13 com r14 com r15 eor r4,r12 eor r5,r13 eor r6,r14 eor r7,r15 eor r12,r8 eor r13,r9 eor r14,r10 eor r15,r11 mov r0,r22 or r0,r4 eor r8,r0 mov r0,r23 or r0,r5 eor r9,r0 mov r0,r2 or r0,r6 eor r10,r0 mov r0,r3 or r0,r7 eor r11,r0 mov r0,r4 and r0,r12 eor r22,r0 mov r0,r5 and r0,r13 eor r23,r0 mov r0,r6 and r0,r14 eor r2,r0 mov r0,r7 and r0,r15 eor r3,r0 mov r0,r22 and r0,r8 eor r4,r0 mov r0,r23 and r0,r9 eor r5,r0 mov r0,r2 and r0,r10 eor r6,r0 mov r0,r3 and r0,r11 eor r7,r0 dec r30 #if defined(RAMPZ) elpm r21,Z #elif defined(__AVR_HAVE_LPMX__) lpm r21,Z #elif defined(__AVR_TINY__) ld r21,Z #else lpm mov r21,r0 #endif dec r30 #if defined(RAMPZ) elpm r20,Z #elif defined(__AVR_HAVE_LPMX__) lpm r20,Z #elif defined(__AVR_TINY__) ld r20,Z #else lpm mov r20,r0 #endif dec r30 #if defined(RAMPZ) elpm r19,Z #elif defined(__AVR_HAVE_LPMX__) lpm r19,Z #elif defined(__AVR_TINY__) ld r19,Z #else lpm mov r19,r0 #endif dec r30 #if defined(RAMPZ) elpm r18,Z #elif defined(__AVR_HAVE_LPMX__) lpm r18,Z #elif defined(__AVR_TINY__) ld r18,Z #else lpm mov r18,r0 #endif eor r12,r18 eor r13,r19 eor r14,r20 eor r15,r21 ld r21,-X ld r20,-X ld r19,-X ld r18,-X eor r8,r18 eor r9,r19 eor r10,r20 eor r11,r21 ld r21,-X ld r20,-X ld r19,-X ld r18,-X eor r4,r18 eor r5,r19 eor r6,r20 eor r7,r21 mov r0,r1 lsr r22 ror r0 lsr r22 ror r0 or r22,r0 mov r0,r1 lsr r23 ror r0 lsr r23 ror r0 or r23,r0 mov r0,r1 lsr r2 ror r0 lsr r2 ror r0 or r2,r0 mov r0,r1 lsr r3 ror r0 lsr r3 ror r0 or r3,r0 swap r4 swap r5 swap r6 swap r7 lsl r8 adc r8,r1 lsl r8 adc r8,r1 lsl r9 adc r9,r1 lsl r9 adc r9,r1 lsl r10 adc r10,r1 lsl r10 adc r10,r1 lsl r11 adc r11,r1 lsl r11 adc r11,r1 mov r0,r12 and r0,r4 eor r8,r0 mov r0,r13 and r0,r5 eor r9,r0 mov r0,r14 and r0,r6 eor r10,r0 mov r0,r15 and r0,r7 eor r11,r0 com r22 com r23 com r2 com r3 eor r4,r22 eor r5,r23 eor r6,r2 eor r7,r3 eor r22,r8 eor r23,r9 eor r2,r10 eor r3,r11 mov r0,r12 or r0,r4 eor r8,r0 mov r0,r13 or r0,r5 eor r9,r0 mov r0,r14 or r0,r6 eor r10,r0 mov r0,r15 or r0,r7 eor r11,r0 mov r0,r4 and r0,r22 eor r12,r0 mov r0,r5 and r0,r23 eor r13,r0 mov r0,r6 and r0,r2 eor r14,r0 mov r0,r7 and r0,r3 eor r15,r0 mov r0,r12 and r0,r8 eor r4,r0 mov r0,r13 and r0,r9 eor r5,r0 mov r0,r14 and r0,r10 eor r6,r0 mov r0,r15 and r0,r11 eor r7,r0 dec r30 #if defined(RAMPZ) elpm r21,Z #elif defined(__AVR_HAVE_LPMX__) lpm r21,Z #elif defined(__AVR_TINY__) ld r21,Z #else lpm mov r21,r0 #endif dec r30 #if defined(RAMPZ) elpm r20,Z #elif defined(__AVR_HAVE_LPMX__) lpm r20,Z #elif defined(__AVR_TINY__) ld r20,Z #else lpm mov r20,r0 #endif dec r30 #if defined(RAMPZ) elpm r19,Z #elif defined(__AVR_HAVE_LPMX__) lpm r19,Z #elif defined(__AVR_TINY__) ld r19,Z #else lpm mov r19,r0 #endif dec r30 #if defined(RAMPZ) elpm r18,Z #elif defined(__AVR_HAVE_LPMX__) lpm r18,Z #elif defined(__AVR_TINY__) ld r18,Z #else lpm mov r18,r0 #endif eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 ld r21,-X ld r20,-X ld r19,-X ld r18,-X eor r8,r18 eor r9,r19 eor r10,r20 eor r11,r21 ld r21,-X ld r20,-X ld r19,-X ld r18,-X eor r4,r18 eor r5,r19 eor r6,r20 eor r7,r21 movw r18,r4 movw r20,r6 lsr r21 ror r20 ror r19 ror r18 eor r18,r4 eor r19,r5 eor r20,r6 eor r21,r7 andi r18,85 andi r19,85 andi r20,85 andi r21,85 eor r4,r18 eor r5,r19 eor r6,r20 eor r7,r21 lsl r18 rol r19 rol r20 rol r21 eor r4,r18 eor r5,r19 eor r6,r20 eor r7,r21 movw r18,r8 movw r20,r10 lsr r21 ror r20 ror r19 ror r18 eor r18,r8 eor r19,r9 andi r18,85 andi r19,85 eor r8,r18 eor r9,r19 mov r20,r1 mov r21,r1 lsl r18 rol r19 rol r20 rol r21 eor r8,r18 eor r9,r19 eor r10,r20 eor r11,r21 mov r0,r10 mov r10,r8 mov r8,r0 mov r0,r11 mov r11,r9 mov r9,r0 movw r18,r14 lsr r19 ror r18 eor r18,r14 eor r19,r15 andi r18,85 andi r19,85 eor r14,r18 eor r15,r19 lsl r18 rol r19 eor r14,r18 eor r15,r19 mov r0,r14 mov r14,r12 mov r12,r0 mov r0,r15 mov r15,r13 mov r13,r0 mov r0,r22 and r0,r4 eor r8,r0 mov r0,r23 and r0,r5 eor r9,r0 mov r0,r2 and r0,r6 eor r10,r0 mov r0,r3 and r0,r7 eor r11,r0 com r12 com r13 com r14 com r15 eor r4,r12 eor r5,r13 eor r6,r14 eor r7,r15 eor r12,r8 eor r13,r9 eor r14,r10 eor r15,r11 mov r0,r22 or r0,r4 eor r8,r0 mov r0,r23 or r0,r5 eor r9,r0 mov r0,r2 or r0,r6 eor r10,r0 mov r0,r3 or r0,r7 eor r11,r0 mov r0,r4 and r0,r12 eor r22,r0 mov r0,r5 and r0,r13 eor r23,r0 mov r0,r6 and r0,r14 eor r2,r0 mov r0,r7 and r0,r15 eor r3,r0 mov r0,r22 and r0,r8 eor r4,r0 mov r0,r23 and r0,r9 eor r5,r0 mov r0,r2 and r0,r10 eor r6,r0 mov r0,r3 and r0,r11 eor r7,r0 dec r30 #if defined(RAMPZ) elpm r21,Z #elif defined(__AVR_HAVE_LPMX__) lpm r21,Z #elif defined(__AVR_TINY__) ld r21,Z #else lpm mov r21,r0 #endif dec r30 #if defined(RAMPZ) elpm r20,Z #elif defined(__AVR_HAVE_LPMX__) lpm r20,Z #elif defined(__AVR_TINY__) ld r20,Z #else lpm mov r20,r0 #endif dec r30 #if defined(RAMPZ) elpm r19,Z #elif defined(__AVR_HAVE_LPMX__) lpm r19,Z #elif defined(__AVR_TINY__) ld r19,Z #else lpm mov r19,r0 #endif dec r30 #if defined(RAMPZ) elpm r18,Z #elif defined(__AVR_HAVE_LPMX__) lpm r18,Z #elif defined(__AVR_TINY__) ld r18,Z #else lpm mov r18,r0 #endif eor r12,r18 eor r13,r19 eor r14,r20 eor r15,r21 ld r21,-X ld r20,-X ld r19,-X ld r18,-X eor r8,r18 eor r9,r19 eor r10,r20 eor r11,r21 ld r21,-X ld r20,-X ld r19,-X ld r18,-X eor r4,r18 eor r5,r19 eor r6,r20 eor r7,r21 lsl r22 rol r23 adc r22,r1 lsl r22 rol r23 adc r22,r1 lsl r22 rol r23 adc r22,r1 lsl r22 rol r23 adc r22,r1 lsl r2 rol r3 adc r2,r1 lsl r2 rol r3 adc r2,r1 lsl r2 rol r3 adc r2,r1 lsl r2 rol r3 adc r2,r1 mov r0,r5 mov r5,r4 mov r4,r0 mov r0,r7 mov r7,r6 mov r6,r0 mov r0,r1 lsr r9 ror r8 ror r0 lsr r9 ror r8 ror r0 lsr r9 ror r8 ror r0 lsr r9 ror r8 ror r0 or r9,r0 mov r0,r1 lsr r11 ror r10 ror r0 lsr r11 ror r10 ror r0 lsr r11 ror r10 ror r0 lsr r11 ror r10 ror r0 or r11,r0 mov r0,r12 and r0,r4 eor r8,r0 mov r0,r13 and r0,r5 eor r9,r0 mov r0,r14 and r0,r6 eor r10,r0 mov r0,r15 and r0,r7 eor r11,r0 com r22 com r23 com r2 com r3 eor r4,r22 eor r5,r23 eor r6,r2 eor r7,r3 eor r22,r8 eor r23,r9 eor r2,r10 eor r3,r11 mov r0,r12 or r0,r4 eor r8,r0 mov r0,r13 or r0,r5 eor r9,r0 mov r0,r14 or r0,r6 eor r10,r0 mov r0,r15 or r0,r7 eor r11,r0 mov r0,r4 and r0,r22 eor r12,r0 mov r0,r5 and r0,r23 eor r13,r0 mov r0,r6 and r0,r2 eor r14,r0 mov r0,r7 and r0,r3 eor r15,r0 mov r0,r12 and r0,r8 eor r4,r0 mov r0,r13 and r0,r9 eor r5,r0 mov r0,r14 and r0,r10 eor r6,r0 mov r0,r15 and r0,r11 eor r7,r0 dec r30 #if defined(RAMPZ) elpm r21,Z #elif defined(__AVR_HAVE_LPMX__) lpm r21,Z #elif defined(__AVR_TINY__) ld r21,Z #else lpm mov r21,r0 #endif dec r30 #if defined(RAMPZ) elpm r20,Z #elif defined(__AVR_HAVE_LPMX__) lpm r20,Z #elif defined(__AVR_TINY__) ld r20,Z #else lpm mov r20,r0 #endif dec r30 #if defined(RAMPZ) elpm r19,Z #elif defined(__AVR_HAVE_LPMX__) lpm r19,Z #elif defined(__AVR_TINY__) ld r19,Z #else lpm mov r19,r0 #endif dec r30 #if defined(RAMPZ) elpm r18,Z #elif defined(__AVR_HAVE_LPMX__) lpm r18,Z #elif defined(__AVR_TINY__) ld r18,Z #else lpm mov r18,r0 #endif eor r22,r18 eor r23,r19 eor r2,r20 eor r3,r21 ld r21,-X ld r20,-X ld r19,-X ld r18,-X eor r8,r18 eor r9,r19 eor r10,r20 eor r11,r21 ld r21,-X ld r20,-X ld r19,-X ld r18,-X eor r4,r18 eor r5,r19 eor r6,r20 eor r7,r21 movw r18,r4 movw r20,r6 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 andi r18,204 andi r19,204 andi r20,204 andi r21,204 lsr r7 ror r6 ror r5 ror r4 lsr r7 ror r6 ror r5 ror r4 ldi r25,51 and r4,r25 and r5,r25 and r6,r25 and r7,r25 or r4,r18 or r5,r19 or r6,r20 or r7,r21 movw r18,r8 movw r20,r10 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 lsl r18 rol r19 rol r20 rol r21 andi r18,136 andi r19,136 andi r20,136 andi r21,136 lsr r11 ror r10 ror r9 ror r8 ldi r24,119 and r8,r24 and r9,r24 and r10,r24 and r11,r24 or r8,r18 or r9,r19 or r10,r20 or r11,r21 movw r18,r12 movw r20,r14 lsl r18 rol r19 rol r20 rol r21 andi r18,238 andi r19,238 andi r20,238 andi r21,238 lsr r15 ror r14 ror r13 ror r12 lsr r15 ror r14 ror r13 ror r12 lsr r15 ror r14 ror r13 ror r12 ldi r17,17 and r12,r17 and r13,r17 and r14,r17 and r15,r17 or r12,r18 or r13,r19 or r14,r20 or r15,r21 mov r0,r22 and r0,r4 eor r8,r0 mov r0,r23 and r0,r5 eor r9,r0 mov r0,r2 and r0,r6 eor r10,r0 mov r0,r3 and r0,r7 eor r11,r0 com r12 com r13 com r14 com r15 eor r4,r12 eor r5,r13 eor r6,r14 eor r7,r15 eor r12,r8 eor r13,r9 eor r14,r10 eor r15,r11 mov r0,r22 or r0,r4 eor r8,r0 mov r0,r23 or r0,r5 eor r9,r0 mov r0,r2 or r0,r6 eor r10,r0 mov r0,r3 or r0,r7 eor r11,r0 mov r0,r4 and r0,r12 eor r22,r0 mov r0,r5 and r0,r13 eor r23,r0 mov r0,r6 and r0,r14 eor r2,r0 mov r0,r7 and r0,r15 eor r3,r0 mov r0,r22 and r0,r8 eor r4,r0 mov r0,r23 and r0,r9 eor r5,r0 mov r0,r2 and r0,r10 eor r6,r0 mov r0,r3 and r0,r11 eor r7,r0 ret 768: #if defined(RAMPZ) pop r0 out _SFR_IO_ADDR(RAMPZ),r0 #endif ldd r26,Y+1 ldd r27,Y+2 st X+,r3 st X+,r2 st X+,r23 st X+,r22 st X+,r7 st X+,r6 st X+,r5 st X+,r4 st X+,r11 st X+,r10 st X+,r9 st X+,r8 st X+,r15 st X+,r14 st X+,r13 st X+,r12 pop r0 pop r0 pop r17 pop r15 pop r14 pop r13 pop r12 pop r11 pop r10 pop r9 pop r8 pop r7 pop r6 pop r5 pop r4 pop r3 pop r2 pop r29 pop r28 ret .size gift128b_decrypt, .-gift128b_decrypt #endif #endif