verilog.log

OSS_CVC_7.00b-x86_64-rhel6x of 07/07/14 (Linux-elf).
Copyright (c) 1991-2014 Tachyon Design Automation Corp.
  All Rights reserved.  Licensed software subject to prohibitions and
  restrictions.  See OSS CVC artistic license included with release.
Today is Sun Mar 24 22:40:37 2019.
Elaborating source file "tb_wrapper.v"
Elaborating source file "wrapper.v"
Elaborating source file "drygascon128_use_funcs.v"
Highest level modules:
tb_wrapper

sim pass
Halted at location **tb_wrapper.v(389) time 322640000 ps from call to $finish.
  There were 0 error(s), 0 warning(s), and 107 inform(s).