sb_64.vhd

-- This work is licensed under a Creative Commons
-- Attribution-NonCommercial-ShareAlike 4.0 International License.
-- http://creativecommons.org/licenses/by-nc-sa/4.0

-- Mark D. Aagaard
-- Riham AlTawy
-- Guang Gong
-- Kalikinkar Mandal
-- Raghvendra Rohit
-- Marat Sattarov
-- http://comsec.uwaterloo.ca


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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ace_pkg.all;

entity sb_64 is
  port
    ( i_state : in  word
    ; i_rc    : in  std_logic
    ; o_state : out word
    );
end entity;

architecture rtl of sb_64 is
  signal x0, x1, z0, z1 : half_word;
  signal rc : half_word;
begin

  x1 <= i_state(            0 to half_word_sz-1 );
  x0 <= i_state( half_word_sz to word_sz - 1    );

  rc <= ( 0 to half_word_sz - 2 => '1', half_word_sz - 1 => i_rc ); 

  z0 <= x1;
  z1 <=    ( ( x1(5 to half_word_sz - 1) & x1 (0 to 4) ) and x1)
        xor (  x1(1 to half_word_sz - 1) & x1 (0)      )
        xor x0
        xor rc;
          
          
  o_state <= z1 & z0;

end architecture;