ace-rtl.vhd

-- This work is licensed under a Creative Commons
-- Attribution-NonCommercial-ShareAlike 4.0 International License.
-- http://creativecommons.org/licenses/by-nc-sa/4.0

-- Mark D. Aagaard
-- Riham AlTawy
-- Guang Gong
-- Kalikinkar Mandal
-- Raghvendra Rohit
-- Marat Sattarov
-- http://comsec.uwaterloo.ca


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architecture rtl of ace is
  signal ctl_control    : ace_ctl_ty;
  signal ctl_onehot     : onehot_ty;
  signal ctl_lfsr_en    : std_logic;
  signal ctl_lfsr_reset : std_logic;
begin

  u_dp :
    entity work.dp port map
      ( clk       => clk
      , reset     => reset
      , i_mode    => i_mode
      , i_control => ctl_control
      , i_onehot  => ctl_onehot    
      , i_dom_sep => i_dom_sep
      , i_valid   => i_valid
      , i_data    => i_data
      , i_padding => i_padding
      , o_data    => o_data
     );

  u_ctl :
    entity work.ctl port map
      ( clk          => clk
      , reset        => reset
      , i_mode       => i_mode
      , i_dom_sep    => i_dom_sep
      , i_valid      => i_valid
      , i_padding    => i_padding
      , o_valid      => o_valid
      , o_onehot     => ctl_onehot
      , o_ready      => o_ready
      , o_control    => ctl_control
     );

end architecture;